890 lines
30 KiB
Verilog
890 lines
30 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_instruction_unit.v
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// Title : Instruction unit
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : Support for static branch prediction is added. Fetching of
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// : instructions can also be altered by branches predicted in D
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// : stage of pipeline, and mispredicted branches in the X and M
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// : stages of the pipeline.
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// Version : 3.2
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// : EBRs use SYNC resets instead of ASYNC resets.
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// Version : 3.3
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// : Support for a non-cacheable Instruction Memory that has a
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// : single-cycle access latency. This memory can be accessed by
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// : data port of LM32 (so that debugger has access to it).
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// Version : 3.4
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// : No change
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// Version : 3.5
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// : Bug fix: Inline memory is correctly generated if it is not a
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// : power-of-two.
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// : Bug fix: Fixed a bug that caused LM32 (configured without
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// : instruction cache) to lock up in to an infinite loop due to a
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// : instruction bus error when EBA was set to instruction inline
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// : memory.
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// Version : 3.8
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// : Feature: Support for dynamically switching EBA to DEBA via a
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// : GPIO.
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_instruction_unit (
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// ----- Inputs -------
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clk_i,
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rst_i,
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_ALTERNATE_EBA
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at_debug,
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`endif
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`endif
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// From pipeline
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stall_a,
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stall_f,
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stall_d,
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stall_x,
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stall_m,
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valid_f,
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valid_d,
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kill_f,
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branch_predict_taken_d,
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branch_predict_address_d,
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`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
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branch_taken_x,
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branch_target_x,
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`endif
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exception_m,
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branch_taken_m,
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branch_mispredict_taken_m,
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branch_target_m,
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`ifdef CFG_ICACHE_ENABLED
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iflush,
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`endif
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`ifdef CFG_DCACHE_ENABLED
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dcache_restart_request,
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dcache_refill_request,
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dcache_refilling,
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`endif
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`ifdef CFG_IROM_ENABLED
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irom_store_data_m,
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irom_address_xm,
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irom_we_xm,
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`endif
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`ifdef CFG_IWB_ENABLED
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// From Wishbone
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i_dat_i,
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i_ack_i,
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i_err_i,
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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jtag_read_enable,
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jtag_write_enable,
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jtag_write_data,
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jtag_address,
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`endif
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// ----- Outputs -------
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// To pipeline
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pc_f,
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pc_d,
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pc_x,
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pc_m,
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pc_w,
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`ifdef CFG_ICACHE_ENABLED
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icache_stall_request,
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icache_restart_request,
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icache_refill_request,
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icache_refilling,
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`endif
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`ifdef CFG_IROM_ENABLED
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irom_data_m,
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`endif
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`ifdef CFG_IWB_ENABLED
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// To Wishbone
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i_dat_o,
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i_adr_o,
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i_cyc_o,
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i_sel_o,
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i_stb_o,
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i_we_o,
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i_cti_o,
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i_lock_o,
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i_bte_o,
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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jtag_read_data,
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jtag_access_complete,
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`endif
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`ifdef CFG_BUS_ERRORS_ENABLED
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bus_error_d,
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`endif
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`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
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instruction_f,
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`endif
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instruction_d
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);
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/////////////////////////////////////////////////////
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// Parameters
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/////////////////////////////////////////////////////
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parameter associativity = 1; // Associativity of the cache (Number of ways)
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parameter sets = 512; // Number of sets
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parameter bytes_per_line = 16; // Number of bytes per cache line
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parameter base_address = 0; // Base address of cachable memory
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parameter limit = 0; // Limit (highest address) of cachable memory
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// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
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localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_ALTERNATE_EBA
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input at_debug; // GPIO input that maps EBA to DEBA
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`endif
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`endif
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input stall_a; // Stall A stage instruction
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input stall_f; // Stall F stage instruction
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input stall_d; // Stall D stage instruction
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input stall_x; // Stall X stage instruction
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input stall_m; // Stall M stage instruction
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input valid_f; // Instruction in F stage is valid
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input valid_d; // Instruction in D stage is valid
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input kill_f; // Kill instruction in F stage
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input branch_predict_taken_d; // Branch is predicted taken in D stage
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input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address
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`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
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input branch_taken_x; // Branch instruction in X stage is taken
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input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
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`endif
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input exception_m;
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input branch_taken_m; // Branch instruction in M stage is taken
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input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken
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input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
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`ifdef CFG_ICACHE_ENABLED
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input iflush; // Flush instruction cache
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`endif
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`ifdef CFG_DCACHE_ENABLED
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input dcache_restart_request; // Restart instruction that caused a data cache miss
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input dcache_refill_request; // Request to refill data cache
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input dcache_refilling;
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`endif
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`ifdef CFG_IROM_ENABLED
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input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit
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input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit
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input irom_we_xm; // Indicates if memory operation is load or store
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`endif
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`ifdef CFG_IWB_ENABLED
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input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
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input i_ack_i; // Instruction Wishbone interface acknowledgement
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input i_err_i; // Instruction Wishbone interface error
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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input jtag_read_enable; // JTAG read memory request
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input jtag_write_enable; // JTAG write memory request
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input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
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input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
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`endif
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output [`LM32_PC_RNG] pc_f; // F stage PC
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reg [`LM32_PC_RNG] pc_f;
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output [`LM32_PC_RNG] pc_d; // D stage PC
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reg [`LM32_PC_RNG] pc_d;
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output [`LM32_PC_RNG] pc_x; // X stage PC
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reg [`LM32_PC_RNG] pc_x;
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output [`LM32_PC_RNG] pc_m; // M stage PC
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reg [`LM32_PC_RNG] pc_m;
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output [`LM32_PC_RNG] pc_w; // W stage PC
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reg [`LM32_PC_RNG] pc_w;
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`ifdef CFG_ICACHE_ENABLED
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output icache_stall_request; // Instruction cache stall request
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wire icache_stall_request;
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output icache_restart_request; // Request to restart instruction that cached instruction cache miss
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wire icache_restart_request;
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output icache_refill_request; // Instruction cache refill request
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wire icache_refill_request;
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output icache_refilling; // Indicates the icache is refilling
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wire icache_refilling;
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`endif
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`ifdef CFG_IROM_ENABLED
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output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load
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wire [`LM32_WORD_RNG] irom_data_m;
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`endif
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`ifdef CFG_IWB_ENABLED
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output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
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`ifdef CFG_HW_DEBUG_ENABLED
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reg [`LM32_WORD_RNG] i_dat_o;
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`else
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wire [`LM32_WORD_RNG] i_dat_o;
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`endif
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output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
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reg [`LM32_WORD_RNG] i_adr_o;
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output i_cyc_o; // Instruction Wishbone interface cycle
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reg i_cyc_o;
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output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
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`ifdef CFG_HW_DEBUG_ENABLED
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reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
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`else
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wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
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`endif
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output i_stb_o; // Instruction Wishbone interface strobe
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reg i_stb_o;
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output i_we_o; // Instruction Wishbone interface write enable
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`ifdef CFG_HW_DEBUG_ENABLED
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reg i_we_o;
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`else
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wire i_we_o;
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`endif
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output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
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reg [`LM32_CTYPE_RNG] i_cti_o;
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output i_lock_o; // Instruction Wishbone interface lock bus
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reg i_lock_o;
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output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
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wire [`LM32_BTYPE_RNG] i_bte_o;
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
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reg [`LM32_BYTE_RNG] jtag_read_data;
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output jtag_access_complete; // Requested memory access by JTAG interface is complete
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wire jtag_access_complete;
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`endif
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`ifdef CFG_BUS_ERRORS_ENABLED
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output bus_error_d; // Indicates a bus error occured while fetching the instruction
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reg bus_error_d;
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`endif
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`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
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output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
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wire [`LM32_INSTRUCTION_RNG] instruction_f;
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`endif
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output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
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reg [`LM32_INSTRUCTION_RNG] instruction_d;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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reg [`LM32_PC_RNG] pc_a; // A stage PC
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`ifdef LM32_CACHE_ENABLED
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reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
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`endif
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`ifdef CFG_ICACHE_ENABLED
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wire icache_read_enable_f; // Indicates if instruction cache miss is valid
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wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
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reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
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reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
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wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
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wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
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wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
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wire last_word; // Indicates if this is the last word in the cache line
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wire [`LM32_PC_RNG] first_address; // First cache refill address
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`else
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`ifdef CFG_IWB_ENABLED
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reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
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`endif
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`endif
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`ifdef CFG_IROM_ENABLED
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wire irom_select_a; // Indicates if A stage PC maps to a ROM address
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reg irom_select_f; // Indicates if F stage PC maps to a ROM address
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wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
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`endif
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`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
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`else
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wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
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`endif
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`ifdef CFG_BUS_ERRORS_ENABLED
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reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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reg jtag_access; // Indicates if a JTAG WB access is in progress
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`endif
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`ifdef CFG_ALTERNATE_EBA
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reg alternate_eba_taken;
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`endif
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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// Instruction ROM
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`ifdef CFG_IROM_ENABLED
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pmi_ram_dp_true
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#(
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// ----- Parameters -------
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.pmi_family (`LATTICE_FAMILY),
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//.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_data_width_a (`LM32_WORD_WIDTH),
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//.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
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//.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
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.pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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.pmi_data_width_a (`LM32_WORD_WIDTH),
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.pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
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.pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
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.pmi_data_width_b (`LM32_WORD_WIDTH),
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.pmi_regmode_a ("noreg"),
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.pmi_regmode_b ("noreg"),
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.pmi_gsr ("enable"),
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.pmi_resetmode ("sync"),
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.pmi_init_file (`CFG_IROM_INIT_FILE),
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.pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT),
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.module_type ("pmi_ram_dp_true")
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)
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ram (
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// ----- Inputs -------
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.ClockA (clk_i),
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.ClockB (clk_i),
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.ResetA (rst_i),
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.ResetB (rst_i),
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.DataInA ({32{1'b0}}),
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.DataInB (irom_store_data_m),
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.AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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.AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
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.ClockEnA (!stall_a),
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.ClockEnB (!stall_x || !stall_m),
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.WrA (`FALSE),
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.WrB (irom_we_xm),
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// ----- Outputs -------
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.QA (irom_data_f),
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.QB (irom_data_m)
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);
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`endif
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`ifdef CFG_ICACHE_ENABLED
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// Instruction cache
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lm32_icache #(
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.associativity (associativity),
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.sets (sets),
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.bytes_per_line (bytes_per_line),
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.base_address (base_address),
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.limit (limit)
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) icache (
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// ----- Inputs -----
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.clk_i (clk_i),
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.rst_i (rst_i),
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.stall_a (stall_a),
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.stall_f (stall_f),
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.branch_predict_taken_d (branch_predict_taken_d),
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.valid_d (valid_d),
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.address_a (pc_a),
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.address_f (pc_f),
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.read_enable_f (icache_read_enable_f),
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.refill_ready (icache_refill_ready),
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.refill_data (icache_refill_data),
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.iflush (iflush),
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// ----- Outputs -----
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.stall_request (icache_stall_request),
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.restart_request (icache_restart_request),
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.refill_request (icache_refill_request),
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.refill_address (icache_refill_address),
|
|
.refilling (icache_refilling),
|
|
.inst (icache_data_f)
|
|
);
|
|
`endif
|
|
|
|
/////////////////////////////////////////////////////
|
|
// Combinational Logic
|
|
/////////////////////////////////////////////////////
|
|
|
|
`ifdef CFG_ICACHE_ENABLED
|
|
// Generate signal that indicates when instruction cache misses are valid
|
|
assign icache_read_enable_f = (valid_f == `TRUE)
|
|
&& (kill_f == `FALSE)
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
&& (dcache_restart_request == `FALSE)
|
|
`endif
|
|
`ifdef CFG_IROM_ENABLED
|
|
&& (irom_select_f == `FALSE)
|
|
`endif
|
|
;
|
|
`endif
|
|
|
|
// Compute address of next instruction to fetch
|
|
always @(*)
|
|
begin
|
|
// The request from the latest pipeline stage must take priority
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
if (dcache_restart_request == `TRUE)
|
|
pc_a = restart_address;
|
|
else
|
|
`endif
|
|
if (branch_taken_m == `TRUE)
|
|
if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
|
|
pc_a = pc_x;
|
|
else
|
|
pc_a = branch_target_m;
|
|
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|
|
else if (branch_taken_x == `TRUE)
|
|
pc_a = branch_target_x;
|
|
`endif
|
|
else
|
|
if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
|
|
pc_a = branch_predict_address_d;
|
|
else
|
|
`ifdef CFG_ICACHE_ENABLED
|
|
if (icache_restart_request == `TRUE)
|
|
pc_a = restart_address;
|
|
else
|
|
`endif
|
|
pc_a = pc_f + 1'b1;
|
|
end
|
|
|
|
// Select where instruction should be fetched from
|
|
`ifdef CFG_IROM_ENABLED
|
|
assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
|
|
`endif
|
|
|
|
// Select instruction from selected source
|
|
`ifdef CFG_ICACHE_ENABLED
|
|
`ifdef CFG_IROM_ENABLED
|
|
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
|
|
`else
|
|
assign instruction_f = icache_data_f;
|
|
`endif
|
|
`else
|
|
`ifdef CFG_IROM_ENABLED
|
|
`ifdef CFG_IWB_ENABLED
|
|
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
|
|
`else
|
|
assign instruction_f = irom_data_f;
|
|
`endif
|
|
`else
|
|
assign instruction_f = wb_data_f;
|
|
`endif
|
|
`endif
|
|
|
|
// Unused/constant Wishbone signals
|
|
`ifdef CFG_IWB_ENABLED
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
|
`else
|
|
assign i_dat_o = 32'd0;
|
|
assign i_we_o = `FALSE;
|
|
assign i_sel_o = 4'b1111;
|
|
`endif
|
|
assign i_bte_o = `LM32_BTYPE_LINEAR;
|
|
`endif
|
|
|
|
`ifdef CFG_ICACHE_ENABLED
|
|
// Determine parameters for next cache refill Wishbone access
|
|
generate
|
|
case (bytes_per_line)
|
|
4:
|
|
begin
|
|
assign first_cycle_type = `LM32_CTYPE_END;
|
|
assign next_cycle_type = `LM32_CTYPE_END;
|
|
assign last_word = `TRUE;
|
|
assign first_address = icache_refill_address;
|
|
end
|
|
8:
|
|
begin
|
|
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
|
assign next_cycle_type = `LM32_CTYPE_END;
|
|
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
|
|
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
|
|
end
|
|
16:
|
|
begin
|
|
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
|
assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
|
|
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
|
|
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
|
|
end
|
|
endcase
|
|
endgenerate
|
|
`endif
|
|
|
|
/////////////////////////////////////////////////////
|
|
// Sequential Logic
|
|
/////////////////////////////////////////////////////
|
|
|
|
// PC
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
begin
|
|
`ifdef CFG_DEBUG_ENABLED
|
|
`ifdef CFG_ALTERNATE_EBA
|
|
if (at_debug == `TRUE)
|
|
pc_f <= (`CFG_DEBA_RESET-4)/4;
|
|
else
|
|
pc_f <= (`CFG_EBA_RESET-4)/4;
|
|
`else
|
|
pc_f <= (`CFG_EBA_RESET-4)/4;
|
|
`endif
|
|
`else
|
|
pc_f <= (`CFG_EBA_RESET-4)/4;
|
|
`endif
|
|
pc_d <= {`LM32_PC_WIDTH{1'b0}};
|
|
pc_x <= {`LM32_PC_WIDTH{1'b0}};
|
|
pc_m <= {`LM32_PC_WIDTH{1'b0}};
|
|
pc_w <= {`LM32_PC_WIDTH{1'b0}};
|
|
end
|
|
else
|
|
begin
|
|
if (stall_f == `FALSE)
|
|
pc_f <= pc_a;
|
|
if (stall_d == `FALSE)
|
|
pc_d <= pc_f;
|
|
if (stall_x == `FALSE)
|
|
pc_x <= pc_d;
|
|
if (stall_m == `FALSE)
|
|
pc_m <= pc_x;
|
|
pc_w <= pc_m;
|
|
end
|
|
end
|
|
|
|
`ifdef LM32_CACHE_ENABLED
|
|
// Address to restart from after a cache miss has been handled
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
restart_address <= {`LM32_PC_WIDTH{1'b0}};
|
|
else
|
|
begin
|
|
`ifdef CFG_DCACHE_ENABLED
|
|
`ifdef CFG_ICACHE_ENABLED
|
|
// D-cache restart address must take priority, otherwise instructions will be lost
|
|
if (dcache_refill_request == `TRUE)
|
|
restart_address <= pc_w;
|
|
else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
|
|
restart_address <= icache_refill_address;
|
|
`else
|
|
if (dcache_refill_request == `TRUE)
|
|
restart_address <= pc_w;
|
|
`endif
|
|
`else
|
|
`ifdef CFG_ICACHE_ENABLED
|
|
if (icache_refill_request == `TRUE)
|
|
restart_address <= icache_refill_address;
|
|
`endif
|
|
`endif
|
|
end
|
|
end
|
|
`endif
|
|
|
|
// Record where instruction was fetched from
|
|
`ifdef CFG_IROM_ENABLED
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
irom_select_f <= `FALSE;
|
|
else
|
|
begin
|
|
if (stall_f == `FALSE)
|
|
irom_select_f <= irom_select_a;
|
|
end
|
|
end
|
|
`endif
|
|
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
|
assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
|
|
always @(*)
|
|
begin
|
|
case (jtag_address[1:0])
|
|
2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
|
|
2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
|
|
2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
|
|
2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
|
|
endcase
|
|
end
|
|
`endif
|
|
|
|
`ifdef CFG_IWB_ENABLED
|
|
// Instruction Wishbone interface
|
|
`ifdef CFG_ICACHE_ENABLED
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
begin
|
|
i_cyc_o <= `FALSE;
|
|
i_stb_o <= `FALSE;
|
|
i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
|
|
i_cti_o <= `LM32_CTYPE_END;
|
|
i_lock_o <= `FALSE;
|
|
icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
|
|
icache_refill_ready <= `FALSE;
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
bus_error_f <= `FALSE;
|
|
`endif
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
|
i_we_o <= `FALSE;
|
|
i_sel_o <= 4'b1111;
|
|
jtag_access <= `FALSE;
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
icache_refill_ready <= `FALSE;
|
|
// Is a cycle in progress?
|
|
if (i_cyc_o == `TRUE)
|
|
begin
|
|
// Has cycle completed?
|
|
if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
|
|
begin
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
|
if (jtag_access == `TRUE)
|
|
begin
|
|
i_cyc_o <= `FALSE;
|
|
i_stb_o <= `FALSE;
|
|
i_we_o <= `FALSE;
|
|
jtag_access <= `FALSE;
|
|
end
|
|
else
|
|
`endif
|
|
begin
|
|
if (last_word == `TRUE)
|
|
begin
|
|
// Cache line fill complete
|
|
i_cyc_o <= `FALSE;
|
|
i_stb_o <= `FALSE;
|
|
i_lock_o <= `FALSE;
|
|
end
|
|
// Fetch next word in cache line
|
|
i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
|
|
i_cti_o <= next_cycle_type;
|
|
// Write fetched data into instruction cache
|
|
icache_refill_ready <= `TRUE;
|
|
icache_refill_data <= i_dat_i;
|
|
end
|
|
end
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
if (i_err_i == `TRUE)
|
|
begin
|
|
bus_error_f <= `TRUE;
|
|
$display ("Instruction bus error. Address: %x", i_adr_o);
|
|
end
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
|
|
begin
|
|
// Read first word of cache line
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
|
i_sel_o <= 4'b1111;
|
|
`endif
|
|
i_adr_o <= {first_address, 2'b00};
|
|
i_cyc_o <= `TRUE;
|
|
i_stb_o <= `TRUE;
|
|
i_cti_o <= first_cycle_type;
|
|
//i_lock_o <= `TRUE;
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
bus_error_f <= `FALSE;
|
|
`endif
|
|
end
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
|
else
|
|
begin
|
|
if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
|
|
begin
|
|
case (jtag_address[1:0])
|
|
2'b00: i_sel_o <= 4'b1000;
|
|
2'b01: i_sel_o <= 4'b0100;
|
|
2'b10: i_sel_o <= 4'b0010;
|
|
2'b11: i_sel_o <= 4'b0001;
|
|
endcase
|
|
i_adr_o <= jtag_address;
|
|
i_dat_o <= {4{jtag_write_data}};
|
|
i_cyc_o <= `TRUE;
|
|
i_stb_o <= `TRUE;
|
|
i_we_o <= jtag_write_enable;
|
|
i_cti_o <= `LM32_CTYPE_END;
|
|
jtag_access <= `TRUE;
|
|
end
|
|
end
|
|
`endif
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
// Clear bus error when exception taken, otherwise they would be
|
|
// continually generated if exception handler is cached
|
|
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|
|
if (branch_taken_x == `TRUE)
|
|
bus_error_f <= `FALSE;
|
|
`endif
|
|
if (branch_taken_m == `TRUE)
|
|
bus_error_f <= `FALSE;
|
|
`endif
|
|
end
|
|
end
|
|
end
|
|
`else
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
begin
|
|
i_cyc_o <= `FALSE;
|
|
i_stb_o <= `FALSE;
|
|
i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
|
|
i_cti_o <= `LM32_CTYPE_END;
|
|
i_lock_o <= `FALSE;
|
|
wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
bus_error_f <= `FALSE;
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
// Is a cycle in progress?
|
|
if (i_cyc_o == `TRUE)
|
|
begin
|
|
// Has cycle completed?
|
|
if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
|
|
begin
|
|
// Cycle complete
|
|
i_cyc_o <= `FALSE;
|
|
i_stb_o <= `FALSE;
|
|
// Register fetched instruction
|
|
wb_data_f <= i_dat_i;
|
|
end
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
if (i_err_i == `TRUE)
|
|
begin
|
|
bus_error_f <= `TRUE;
|
|
$display ("Instruction bus error. Address: %x", i_adr_o);
|
|
end
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
// Wait for an instruction fetch from an external address
|
|
if ( (stall_a == `FALSE)
|
|
`ifdef CFG_IROM_ENABLED
|
|
&& (irom_select_a == `FALSE)
|
|
`endif
|
|
)
|
|
begin
|
|
// Fetch instruction
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
|
i_sel_o <= 4'b1111;
|
|
`endif
|
|
i_adr_o <= {pc_a, 2'b00};
|
|
i_cyc_o <= `TRUE;
|
|
i_stb_o <= `TRUE;
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
bus_error_f <= `FALSE;
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
if ( (stall_a == `FALSE)
|
|
`ifdef CFG_IROM_ENABLED
|
|
&& (irom_select_a == `TRUE)
|
|
`endif
|
|
)
|
|
begin
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
bus_error_f <= `FALSE;
|
|
`endif
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
`endif
|
|
`endif
|
|
|
|
// Instruction register
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
|
begin
|
|
if (rst_i == `TRUE)
|
|
begin
|
|
instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
bus_error_d <= `FALSE;
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
if (stall_d == `FALSE)
|
|
begin
|
|
instruction_d <= instruction_f;
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
|
bus_error_d <= bus_error_f;
|
|
`endif
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|