499 lines
16 KiB
Verilog
499 lines
16 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_jtag.v
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// Title : JTAG interface
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : No Change
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// =============================================================================
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`include "lm32_include.v"
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`ifdef CFG_JTAG_ENABLED
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`define LM32_DP 3'b000
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`define LM32_TX 3'b001
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`define LM32_RX 3'b010
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// LM32 Debug Protocol commands IDs
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`define LM32_DP_RNG 3:0
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`define LM32_DP_READ_MEMORY 4'b0001
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`define LM32_DP_WRITE_MEMORY 4'b0010
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`define LM32_DP_READ_SEQUENTIAL 4'b0011
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`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
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`define LM32_DP_WRITE_CSR 4'b0101
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`define LM32_DP_BREAK 4'b0110
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`define LM32_DP_RESET 4'b0111
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// States for FSM
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`define LM32_JTAG_STATE_RNG 3:0
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`define LM32_JTAG_STATE_READ_COMMAND 4'h0
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`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
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`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
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`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
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`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
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`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
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`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
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`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
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`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_jtag (
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// ----- Inputs -------
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clk_i,
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rst_i,
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jtag_clk,
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jtag_update,
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jtag_reg_q,
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jtag_reg_addr_q,
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`ifdef CFG_JTAG_UART_ENABLED
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csr,
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csr_write_enable,
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csr_write_data,
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stall_x,
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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jtag_read_data,
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jtag_access_complete,
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`endif
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`ifdef CFG_DEBUG_ENABLED
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exception_q_w,
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`endif
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// ----- Outputs -------
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`ifdef CFG_JTAG_UART_ENABLED
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jtx_csr_read_data,
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jrx_csr_read_data,
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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jtag_csr_write_enable,
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jtag_csr_write_data,
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jtag_csr,
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jtag_read_enable,
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jtag_write_enable,
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jtag_write_data,
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jtag_address,
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`endif
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`ifdef CFG_DEBUG_ENABLED
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jtag_break,
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jtag_reset,
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`endif
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jtag_reg_d,
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jtag_reg_addr_d
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);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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input jtag_clk; // JTAG clock
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input jtag_update; // JTAG data register has been updated
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input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
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input [2:0] jtag_reg_addr_q; // JTAG data register
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`ifdef CFG_JTAG_UART_ENABLED
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input [`LM32_CSR_RNG] csr; // CSR to write
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input csr_write_enable; // CSR write enable
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input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
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input stall_x; // Stall instruction in X stage
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
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input jtag_access_complete; // Memory access if complete
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`endif
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`ifdef CFG_DEBUG_ENABLED
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input exception_q_w; // Indicates an exception has occured in W stage
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`endif
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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`ifdef CFG_JTAG_UART_ENABLED
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output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
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wire [`LM32_WORD_RNG] jtx_csr_read_data;
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output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
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wire [`LM32_WORD_RNG] jrx_csr_read_data;
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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output jtag_csr_write_enable; // CSR write enable
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reg jtag_csr_write_enable;
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output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
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wire [`LM32_WORD_RNG] jtag_csr_write_data;
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output [`LM32_CSR_RNG] jtag_csr; // CSR to write
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wire [`LM32_CSR_RNG] jtag_csr;
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output jtag_read_enable; // Memory read enable
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reg jtag_read_enable;
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output jtag_write_enable; // Memory write enable
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reg jtag_write_enable;
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output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
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wire [`LM32_BYTE_RNG] jtag_write_data;
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output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
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wire [`LM32_WORD_RNG] jtag_address;
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`endif
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`ifdef CFG_DEBUG_ENABLED
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output jtag_break; // Request to raise a breakpoint exception
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reg jtag_break;
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output jtag_reset; // Request to raise a reset exception
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reg jtag_reset;
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`endif
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output [`LM32_BYTE_RNG] jtag_reg_d;
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reg [`LM32_BYTE_RNG] jtag_reg_d;
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output [2:0] jtag_reg_addr_d;
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wire [2:0] jtag_reg_addr_d;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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reg rx_toggle; // Clock-domain crossing registers
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reg rx_toggle_r; // Registered version of rx_toggle
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reg rx_toggle_r_r; // Registered version of rx_toggle_r
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reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r
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reg [`LM32_BYTE_RNG] rx_byte;
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reg [2:0] rx_addr;
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`ifdef CFG_JTAG_UART_ENABLED
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reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
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reg uart_tx_valid; // TX data is valid
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reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
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reg uart_rx_valid; // RX data is valid
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`endif
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reg [`LM32_DP_RNG] command; // The last received command
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`ifdef CFG_HW_DEBUG_ENABLED
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reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
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reg [`LM32_BYTE_RNG] jtag_byte_1;
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reg [`LM32_BYTE_RNG] jtag_byte_2;
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reg [`LM32_BYTE_RNG] jtag_byte_3;
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reg [`LM32_BYTE_RNG] jtag_byte_4;
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reg processing; // Indicates if we're still processing a memory read/write
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`endif
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reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
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/////////////////////////////////////////////////////
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// Combinational Logic
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/////////////////////////////////////////////////////
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`ifdef CFG_HW_DEBUG_ENABLED
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assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
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assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
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assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
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assign jtag_write_data = jtag_byte_4;
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`endif
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// Generate status flags for reading via the JTAG interface
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`ifdef CFG_JTAG_UART_ENABLED
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assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
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`else
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assign jtag_reg_addr_d[1:0] = 2'b00;
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`endif
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`ifdef CFG_HW_DEBUG_ENABLED
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assign jtag_reg_addr_d[2] = processing;
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`else
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assign jtag_reg_addr_d[2] = 1'b0;
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`endif
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`ifdef CFG_JTAG_UART_ENABLED
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assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
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assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
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`endif
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/////////////////////////////////////////////////////
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// Sequential Logic
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/////////////////////////////////////////////////////
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// Toggle a flag when a JTAG write occurs
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always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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rx_toggle <= 1'b0;
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else
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rx_toggle <= ~rx_toggle;
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end
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always @(*)
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begin
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rx_byte = jtag_reg_q;
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rx_addr = jtag_reg_addr_q;
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end
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// Clock domain crossing from JTAG clock domain to CPU clock domain
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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rx_toggle_r <= 1'b0;
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rx_toggle_r_r <= 1'b0;
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rx_toggle_r_r_r <= 1'b0;
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end
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else
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begin
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rx_toggle_r <= rx_toggle;
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rx_toggle_r_r <= rx_toggle_r;
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rx_toggle_r_r_r <= rx_toggle_r_r;
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end
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end
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// LM32 debug protocol state machine
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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state <= `LM32_JTAG_STATE_READ_COMMAND;
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command <= 4'b0000;
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jtag_reg_d <= 8'h00;
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`ifdef CFG_HW_DEBUG_ENABLED
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processing <= `FALSE;
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jtag_csr_write_enable <= `FALSE;
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jtag_read_enable <= `FALSE;
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jtag_write_enable <= `FALSE;
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`endif
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`ifdef CFG_DEBUG_ENABLED
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jtag_break <= `FALSE;
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jtag_reset <= `FALSE;
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`endif
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`ifdef CFG_JTAG_UART_ENABLED
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uart_tx_byte <= 8'h00;
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uart_tx_valid <= `FALSE;
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uart_rx_byte <= 8'h00;
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uart_rx_valid <= `FALSE;
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`endif
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end
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else
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begin
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`ifdef CFG_JTAG_UART_ENABLED
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if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
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begin
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case (csr)
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`LM32_CSR_JTX:
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begin
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// Set flag indicating data is available
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uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
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uart_tx_valid <= `TRUE;
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end
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`LM32_CSR_JRX:
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begin
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// Clear flag indidicating data has been received
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uart_rx_valid <= `FALSE;
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end
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endcase
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end
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`endif
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`ifdef CFG_DEBUG_ENABLED
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// When an exception has occured, clear the requests
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if (exception_q_w == `TRUE)
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begin
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jtag_break <= `FALSE;
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jtag_reset <= `FALSE;
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end
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`endif
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case (state)
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`LM32_JTAG_STATE_READ_COMMAND:
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begin
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// Wait for rx register to toggle which indicates new data is available
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if (rx_toggle_r_r != rx_toggle_r_r_r)
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begin
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command <= rx_byte[7:4];
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case (rx_addr)
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`ifdef CFG_DEBUG_ENABLED
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`LM32_DP:
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begin
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case (rx_byte[7:4])
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`ifdef CFG_HW_DEBUG_ENABLED
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`LM32_DP_READ_MEMORY:
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state <= `LM32_JTAG_STATE_READ_BYTE_0;
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`LM32_DP_READ_SEQUENTIAL:
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begin
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{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
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state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
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end
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`LM32_DP_WRITE_MEMORY:
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state <= `LM32_JTAG_STATE_READ_BYTE_0;
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`LM32_DP_WRITE_SEQUENTIAL:
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begin
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{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
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state <= 5;
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end
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`LM32_DP_WRITE_CSR:
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state <= `LM32_JTAG_STATE_READ_BYTE_0;
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`endif
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`LM32_DP_BREAK:
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begin
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`ifdef CFG_JTAG_UART_ENABLED
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uart_rx_valid <= `FALSE;
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uart_tx_valid <= `FALSE;
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`endif
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jtag_break <= `TRUE;
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end
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`LM32_DP_RESET:
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begin
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`ifdef CFG_JTAG_UART_ENABLED
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uart_rx_valid <= `FALSE;
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uart_tx_valid <= `FALSE;
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`endif
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jtag_reset <= `TRUE;
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end
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endcase
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end
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`endif
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`ifdef CFG_JTAG_UART_ENABLED
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`LM32_TX:
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begin
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uart_rx_byte <= rx_byte;
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uart_rx_valid <= `TRUE;
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end
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`LM32_RX:
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begin
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jtag_reg_d <= uart_tx_byte;
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uart_tx_valid <= `FALSE;
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end
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`endif
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default:
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;
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endcase
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end
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end
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`ifdef CFG_HW_DEBUG_ENABLED
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`LM32_JTAG_STATE_READ_BYTE_0:
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begin
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if (rx_toggle_r_r != rx_toggle_r_r_r)
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begin
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jtag_byte_0 <= rx_byte;
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state <= `LM32_JTAG_STATE_READ_BYTE_1;
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end
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end
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`LM32_JTAG_STATE_READ_BYTE_1:
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begin
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if (rx_toggle_r_r != rx_toggle_r_r_r)
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begin
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jtag_byte_1 <= rx_byte;
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state <= `LM32_JTAG_STATE_READ_BYTE_2;
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end
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end
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`LM32_JTAG_STATE_READ_BYTE_2:
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begin
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if (rx_toggle_r_r != rx_toggle_r_r_r)
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begin
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jtag_byte_2 <= rx_byte;
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state <= `LM32_JTAG_STATE_READ_BYTE_3;
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end
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end
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`LM32_JTAG_STATE_READ_BYTE_3:
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begin
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if (rx_toggle_r_r != rx_toggle_r_r_r)
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begin
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jtag_byte_3 <= rx_byte;
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if (command == `LM32_DP_READ_MEMORY)
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state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
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else
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state <= `LM32_JTAG_STATE_READ_BYTE_4;
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end
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end
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`LM32_JTAG_STATE_READ_BYTE_4:
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begin
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if (rx_toggle_r_r != rx_toggle_r_r_r)
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begin
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jtag_byte_4 <= rx_byte;
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state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
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end
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end
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`LM32_JTAG_STATE_PROCESS_COMMAND:
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begin
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case (command)
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`LM32_DP_READ_MEMORY,
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`LM32_DP_READ_SEQUENTIAL:
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begin
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jtag_read_enable <= `TRUE;
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processing <= `TRUE;
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state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
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end
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`LM32_DP_WRITE_MEMORY,
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`LM32_DP_WRITE_SEQUENTIAL:
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begin
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jtag_write_enable <= `TRUE;
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processing <= `TRUE;
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state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
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end
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`LM32_DP_WRITE_CSR:
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begin
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jtag_csr_write_enable <= `TRUE;
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processing <= `TRUE;
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state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
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end
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endcase
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end
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`LM32_JTAG_STATE_WAIT_FOR_MEMORY:
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begin
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if (jtag_access_complete == `TRUE)
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begin
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jtag_read_enable <= `FALSE;
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jtag_reg_d <= jtag_read_data;
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jtag_write_enable <= `FALSE;
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processing <= `FALSE;
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state <= `LM32_JTAG_STATE_READ_COMMAND;
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end
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end
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`LM32_JTAG_STATE_WAIT_FOR_CSR:
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begin
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jtag_csr_write_enable <= `FALSE;
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processing <= `FALSE;
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state <= `LM32_JTAG_STATE_READ_COMMAND;
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end
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`endif
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endcase
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end
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end
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endmodule
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`endif
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