121 lines
3.8 KiB
Verilog
121 lines
3.8 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_multiplier.v
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// Title : Pipelined multiplier.
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : No Change
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_multiplier (
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// ----- Inputs -----
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clk_i,
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rst_i,
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stall_x,
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stall_m,
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operand_0,
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operand_1,
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// ----- Ouputs -----
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result
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);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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input stall_x; // Stall instruction in X stage
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input stall_m; // Stall instruction in M stage
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input [`LM32_WORD_RNG] operand_0; // Muliplicand
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input [`LM32_WORD_RNG] operand_1; // Multiplier
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output [`LM32_WORD_RNG] result; // Product of multiplication
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reg [`LM32_WORD_RNG] result;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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reg [`LM32_WORD_RNG] muliplicand;
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reg [`LM32_WORD_RNG] multiplier;
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reg [`LM32_WORD_RNG] product;
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/////////////////////////////////////////////////////
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// Sequential logic
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/////////////////////////////////////////////////////
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
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multiplier <= {`LM32_WORD_WIDTH{1'b0}};
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product <= {`LM32_WORD_WIDTH{1'b0}};
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result <= {`LM32_WORD_WIDTH{1'b0}};
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end
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else
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begin
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if (stall_x == `FALSE)
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begin
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muliplicand <= operand_0;
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multiplier <= operand_1;
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end
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if (stall_m == `FALSE)
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product <= muliplicand * multiplier;
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result <= product;
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end
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end
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endmodule
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