425 lines
8.2 KiB
Verilog
425 lines
8.2 KiB
Verilog
/*
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* Milkymist-NG SoC
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* Copyright (C) 2007, 2008, 2009, 2010, 2011, 2012 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module m1crg #(
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parameter in_period = 0.0,
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parameter f_mult = 0,
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parameter f_div = 0,
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parameter clk2x_period = (in_period*f_div)/(2.0*f_mult)
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) (
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input clkin,
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input trigger_reset,
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output sys_clk,
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output reg sys_rst,
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/* Reset off-chip devices */
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output ac97_rst_n,
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output videoin_rst_n,
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output flash_rst_n,
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/* DDR PHY clocks and reset */
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output clk2x_90,
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output clk4x_wr_left,
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output clk4x_wr_strb_left,
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output clk4x_wr_right,
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output clk4x_wr_strb_right,
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output clk4x_rd_left,
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output clk4x_rd_strb_left,
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output clk4x_rd_right,
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output clk4x_rd_strb_right,
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inout rd_clk_lb /* < unconnected clock pin for read clock PLL loopback */
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);
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/*
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* Reset
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*/
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wire reset_n;
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reg [19:0] rst_debounce;
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always @(posedge sys_clk, negedge reset_n) begin
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if(~reset_n) begin
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rst_debounce <= 20'hFFFFF;
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sys_rst <= 1'b1;
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end else begin
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if(trigger_reset)
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rst_debounce <= 20'hFFFFF;
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else if(rst_debounce != 20'd0)
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rst_debounce <= rst_debounce - 20'd1;
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sys_rst <= rst_debounce != 20'd0;
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end
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end
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assign ac97_rst_n = ~sys_rst;
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assign videoin_rst_n = ~sys_rst;
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/*
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* We must release the Flash reset before the system reset
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* because the Flash needs some time to come out of reset
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* and the CPU begins fetching instructions from it
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* as soon as the system reset is released.
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* From datasheet, minimum reset pulse width is 100ns
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* and reset-to-read time is 150ns.
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*/
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reg [7:0] flash_rstcounter;
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always @(posedge sys_clk, negedge reset_n) begin
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if(~reset_n) begin
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flash_rstcounter <= 8'd0;
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end else begin
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if(trigger_reset)
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flash_rstcounter <= 8'd0;
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else if(~flash_rstcounter[7])
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flash_rstcounter <= flash_rstcounter + 8'd1;
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end
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end
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assign flash_rst_n = flash_rstcounter[7];
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/*
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* Clock management. Largely taken from the NWL reference design.
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*/
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wire sdr_clkin;
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wire clkdiv;
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IBUF #(
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.IOSTANDARD("DEFAULT")
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) clk2_iob (
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.I(clkin),
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.O(sdr_clkin)
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);
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BUFIO2 #(
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.DIVIDE(1),
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.DIVIDE_BYPASS("FALSE"),
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.I_INVERT("FALSE")
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) bufio2_inst2 (
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.I(sdr_clkin),
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.IOCLK(),
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.DIVCLK(clkdiv),
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.SERDESSTROBE()
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);
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wire pll1_lckd;
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wire buf_pll1_fb_out;
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wire pll1out0;
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wire pll1out1;
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wire pll1out2;
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wire pll1out3;
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PLL_ADV #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(4*f_mult),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(in_period),
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.CLKIN2_PERIOD(in_period),
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.CLKOUT0_DIVIDE(f_div),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(f_div),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(4*f_div),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_DIVIDE(2*f_div),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(90),
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.CLKOUT4_DIVIDE(7),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(7),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0.0),
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.COMPENSATION("INTERNAL"),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER(0.100),
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.CLK_FEEDBACK("CLKFBOUT"),
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.SIM_DEVICE("SPARTAN6")
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) pll1 (
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.CLKFBDCM(),
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.CLKFBOUT(buf_pll1_fb_out),
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.CLKOUT0(pll1out0), /* < x4 180 clock for transmitter */
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.CLKOUT1(pll1out1), /* < x4 180 clock for transmitter */
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.CLKOUT2(pll1out2), /* < x1 clock for memory controller */
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.CLKOUT3(pll1out3), /* < x2 90 clock to generate memory clock, clock DQS and memory address and control signals. */
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUTDCM0(),
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.CLKOUTDCM1(),
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.CLKOUTDCM2(),
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.CLKOUTDCM3(),
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.CLKOUTDCM4(),
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.CLKOUTDCM5(),
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.DO(),
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.DRDY(),
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.LOCKED(pll1_lckd),
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.CLKFBIN(buf_pll1_fb_out),
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.CLKIN1(clkdiv),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(5'b00000),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'h0000),
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.DWE(1'b0),
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.RST(1'b0),
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.REL(1'b0)
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);
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BUFPLL #(
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.DIVIDE(4)
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) wr_bufpll_left (
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.PLLIN(pll1out0),
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.GCLK(sys_clk),
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.LOCKED(pll1_lckd),
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.IOCLK(clk4x_wr_left),
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.LOCK(),
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.SERDESSTROBE(clk4x_wr_strb_left)
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);
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BUFPLL #(
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.DIVIDE(4)
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) wr_bufpll_right (
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.PLLIN(pll1out1),
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.GCLK(sys_clk),
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.LOCKED(pll1_lckd),
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.IOCLK(clk4x_wr_right),
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.LOCK(),
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.SERDESSTROBE(clk4x_wr_strb_right)
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);
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BUFG bufg_x1(
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.I(pll1out2),
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.O(sys_clk)
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);
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BUFG bufg_x2_2(
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.I(pll1out3),
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.O(clk2x_90)
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);
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/*
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* Generate clk4x_rd. This clock is sourced from clk2x_90.
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* An IODELAY2 element is included in the path of this clock so that
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* any variation in IDELAY element's base delay is compensated when this clock
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* is used to capture read data which also goes through IDELAY element.
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*/
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wire rd_clk_out;
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ODDR2 #(
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.DDR_ALIGNMENT("C0"),
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.INIT(1'b0),
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.SRTYPE("ASYNC")
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) rd_clk_out_inst (
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.Q(rd_clk_out),
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.C0(clk2x_90),
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.C1(~clk2x_90),
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.CE(1'b1),
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.D0(1'b1),
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.D1(1'b0),
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.R(1'b0),
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.S(1'b0)
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);
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wire rd_clk_out_oe_n;
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ODDR2 #(
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.DDR_ALIGNMENT("C0"),
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.INIT(1'b0),
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.SRTYPE("ASYNC")
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) rd_clk_out_oe_inst (
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.Q(rd_clk_out_oe_n),
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.C0(clk2x_90),
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.C1(~clk2x_90),
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.CE(1'b1),
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.D0(1'b0),
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.D1(1'b0),
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.R(1'b0),
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.S(1'b0)
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);
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wire rd_clk_fb;
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/* Dummy pin used for calibration */
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IOBUF rd_clk_loop_back_inst(
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.O(rd_clk_fb),
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.IO(rd_clk_lb),
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.I(rd_clk_out),
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.T(rd_clk_out_oe_n)
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);
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wire rd_clk_fb_dly;
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IODELAY2 #(
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.DATA_RATE("DDR"),
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.IDELAY_VALUE(0),
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.IDELAY2_VALUE(0),
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.IDELAY_MODE("NORMAL"),
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.ODELAY_VALUE(0),
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.IDELAY_TYPE("FIXED"),
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.COUNTER_WRAPAROUND("STAY_AT_LIMIT"),
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.DELAY_SRC("IDATAIN"),
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.SERDES_MODE("NONE"),
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.SIM_TAPDELAY_VALUE(49)
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) iodelay_cm (
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.IDATAIN(rd_clk_fb),
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.TOUT(),
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.DOUT(),
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.T(1'b1),
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.ODATAIN(1'b0),
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.DATAOUT(rd_clk_fb_dly),
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.DATAOUT2(),
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.IOCLK0(1'b0),
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.IOCLK1(1'b0),
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.CLK(1'b0),
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.CAL(1'b0),
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.INC(1'b0),
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.CE(1'b0),
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.RST(1'b0),
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.BUSY()
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);
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wire rd_clk_fb_dly_bufio;
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BUFIO2 #(
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.DIVIDE(1),
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.DIVIDE_BYPASS("FALSE"),
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.I_INVERT("FALSE")
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) bufio2_inst (
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.I(rd_clk_fb_dly),
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.IOCLK(),
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.DIVCLK(rd_clk_fb_dly_bufio),
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.SERDESSTROBE()
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);
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wire pll2_lckd;
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wire buf_pll2_fb_out;
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wire pll2out0;
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wire pll2out1;
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PLL_ADV #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(4),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(clk2x_period),
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.CLKIN2_PERIOD(clk2x_period),
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.CLKOUT0_DIVIDE(2),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_DIVIDE(2),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_DIVIDE(7),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_DIVIDE(7),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_DIVIDE(7),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_DIVIDE(7),
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.CLKOUT5_DUTY_CYCLE (0.5),
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.CLKOUT5_PHASE(0.0),
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.COMPENSATION("INTERNAL"),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER(0.100),
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.CLK_FEEDBACK("CLKFBOUT"),
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.SIM_DEVICE("SPARTAN6")
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) pll2 (
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.CLKFBDCM(),
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.CLKFBOUT(buf_pll2_fb_out),
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.CLKOUT0(pll2out0), /* < x4 clock to capture read data */
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.CLKOUT1(pll2out1), /* < x4 clock to capture read data */
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUTDCM0(),
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.CLKOUTDCM1(),
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.CLKOUTDCM2(),
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.CLKOUTDCM3(),
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.CLKOUTDCM4(),
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.CLKOUTDCM5(),
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.DO(),
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.DRDY(),
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.LOCKED(pll2_lckd),
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.CLKFBIN(buf_pll2_fb_out),
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.CLKIN1(rd_clk_fb_dly_bufio),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(5'b00000),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'h0000),
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.DWE(1'b0),
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.RST(~pll1_lckd),
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.REL(1'b0)
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);
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BUFPLL #(
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.DIVIDE(4)
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) rd_bufpll_left (
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.PLLIN(pll2out0),
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.GCLK(sys_clk),
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.LOCKED(pll2_lckd),
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.IOCLK(clk4x_rd_left),
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.LOCK(),
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.SERDESSTROBE(clk4x_rd_strb_left)
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);
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BUFPLL #(
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.DIVIDE(4)
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) rd_bufpll_right (
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.PLLIN(pll2out1),
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.GCLK(sys_clk),
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.LOCKED(pll2_lckd),
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.IOCLK(clk4x_rd_right),
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.LOCK(),
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.SERDESSTROBE(clk4x_rd_strb_right)
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);
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wire sdram_sys_clk_lock_d16;
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reg sdram_sys_clk_lock_d17;
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/*
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* Async reset generation
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* The reset is de-asserted 16 clocks after both internal clocks are locked.
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*/
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SRL16 reset_delay_sr(
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.CLK(sys_clk),
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.D(pll1_lckd & pll2_lckd),
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.A0(1'b1),
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.A1(1'b1),
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.A2(1'b1),
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.A3(1'b1),
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.Q(sdram_sys_clk_lock_d16)
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);
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always @(posedge sys_clk)
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sdram_sys_clk_lock_d17 <= sdram_sys_clk_lock_d16;
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assign reset_n = sdram_sys_clk_lock_d17;
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endmodule
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