48 lines
1.7 KiB
Plaintext
48 lines
1.7 KiB
Plaintext
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| __| | | | . | | | | | | | . | | _| .'| |
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|_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
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Miscope
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[> Miscope
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------------
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Miscope is a small logic analyzer to embed in an FPGA.
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While free vendor toolchains are generally used by beginners or for prototyping
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(situations where having a logic analyser in the design is generally helpful)
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free toolchains are always provided without the proprietary logic analyzer
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solution... :(
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Based on Migen, Miscope aims to provide a free, portable and flexible
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alternative to vendor's solutions!
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[> Specification:
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Miscope provides Migen cores to embed in the design and Python drivers to control
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the logic analyzer from the Host. Miscope automatically interconnects all cores
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to a CSR bus. When using Python on the Host, no needs to worry aboutcores register
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mapping, importing miscope project gives you direct access to all the cores!
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Miscope produces .vcd output files to be analyzed in your favorite waveform viewer.
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Since Miscope also provides an Uart2Csr bridge, you only need 2 external Rx/Tx pins
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to be ready to debug!
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[> Status:
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Miio & Mila working on board with standard term.
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RLE working on board.
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RangeDetector and EdgeDector terms not tested.
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[> Examples:
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test_Miio : Led & Switch Test controlled by Python Host.
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test_Miia : Logic Analyzer controlled by Python Host.
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[> Contact
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E-mail: florent@enjoy-digital.fr
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