135 lines
3.0 KiB
Python
135 lines
3.0 KiB
Python
from migen.fhdl.structure import *
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from migen.genlib.misc import *
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from migen.genlib.cdc import *
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from migen.bus import csr
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class Spi2Csr(Module):
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def __init__(self, burst_length=8):
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self.a_w = 14
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self.d_w = 8
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self.burst_length = 8
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# Csr interface
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self.csr = csr.Interface()
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# Spi interface
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self.spi_clk = Signal()
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self.spi_cs_n = Signal(reset=1)
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self.spi_mosi = Signal()
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self.spi_miso = Signal()
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###
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# Resychronisation
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clk_synchro = Synchronizer(i=self.spi_clk)
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cs_n_synchro = Synchronizer(i=self.spi_cs_n)
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mosi_synchro = Synchronizer(i=self.spi_mosi)
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self.specials += {clk_synchro, cs_n_synchro, mosi_synchro}
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# Decode
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spi_clk_rising = Signal()
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spi_clk_falling = Signal()
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spi_cs_n_active = Signal()
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spi_mosi_dat = Signal()
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self.specials += RisingEdge(i=clk_synchro.o, o=spi_clk_rising)
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self.specials += FallingEdge(i=clk_synchro.o, o=spi_clk_falling)
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self.sync +=[
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spi_cs_n_active.eq(~cs_n_synchro.o),
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spi_mosi_dat.eq(~mosi_synchro.o),
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]
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#
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# Spi --> Csr
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#
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spi_cnt = Signal(bits_for(self.a_w + self.burst_length*self.d_w))
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spi_addr = Signal(self.a_w)
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spi_w_dat = Signal(self.d_w)
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spi_r_dat = Signal(self.d_w)
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spi_we = Signal()
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spi_re = Signal()
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spi_we_re_done = Signal(reset=1)
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spi_miso_dat = Signal()
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# Re/We Signals Decoding
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first_b = Signal()
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last_b = Signal()
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self.comb +=[
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first_b.eq(spi_cnt[0:bits_for(self.d_w)-1] == 0),
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last_b.eq(spi_cnt[0:bits_for(self.d_w)-1] == 2**(bits_for(self.d_w-1))-1)
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]
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self.sync +=[
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If((spi_cnt >= (self.a_w + self.d_w)) & first_b,
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spi_we.eq(spi_addr[self.a_w-1] & ~spi_we_re_done),
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spi_re.eq(~spi_addr[self.a_w-1] & ~spi_we_re_done),
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spi_we_re_done.eq(1)
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).Elif((spi_cnt >= self.a_w) & first_b,
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spi_re.eq(~spi_addr[self.a_w-1] & ~spi_we_re_done),
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spi_we_re_done.eq(1)
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).Else(
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spi_we.eq(0),
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spi_re.eq(0),
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spi_we_re_done.eq(0)
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)
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]
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# Spi Addr / Data Decoding
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self.sync +=[
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If(~spi_cs_n_active,
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spi_cnt.eq(0),
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).Elif(spi_clk_rising,
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# addr
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If(spi_cnt < self.a_w,
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spi_addr.eq(Cat(spi_mosi_dat,spi_addr[:self.a_w-1]))
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).Elif((spi_cnt >= (self.a_w+self.d_w)) & last_b,
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spi_addr.eq(spi_addr+1)
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).Elif((spi_cnt >= self.a_w) & last_b & (spi_addr[self.a_w-1] == 0),
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spi_addr.eq(spi_addr+1)
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),
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# dat
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If(spi_cnt >= self.a_w,
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spi_w_dat.eq(Cat(spi_mosi_dat,spi_w_dat[:self.d_w-1]))
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),
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# spi_cnt
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spi_cnt.eq(spi_cnt+1)
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)
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]
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#
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# Csr --> Spi
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#
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spi_r_dat_shift = Signal(self.d_w)
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self.sync +=[
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If(spi_re,
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spi_r_dat_shift.eq(spi_r_dat)
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),
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If(~spi_cs_n_active,
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spi_miso_dat.eq(0)
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).Elif(spi_clk_falling,
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spi_miso_dat.eq(spi_r_dat_shift[self.d_w-1]),
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spi_r_dat_shift.eq(Cat(0,spi_r_dat_shift[:self.d_w-1]))
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)
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]
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#
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# Csr Interface
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#
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self.comb += [
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self.csr.adr.eq(spi_addr),
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self.csr.dat_w.eq(spi_w_dat),
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self.csr.we.eq(spi_we)
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]
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#
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# Spi Interface
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#
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self.comb += [
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spi_r_dat.eq(self.csr.dat_r),
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self.spi_miso.eq(spi_miso_dat)
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] |