108 lines
2.2 KiB
Python
108 lines
2.2 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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class UART(Module):
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def __init__(self, clk_freq, baud=115200):
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self.rx_ev = Signal()
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self.rx_dat = Signal(8)
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self.tx_we = Signal()
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self.tx_ev = Signal()
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self.tx_dat = Signal(8)
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self.divisor = Signal(16, reset=int(clk_freq/baud/16))
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self.tx = Signal(reset=1)
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self.rx = Signal()
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###
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enable16 = Signal()
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enable16_counter = Signal(16)
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self.comb += enable16.eq(enable16_counter == 0)
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self.sync += [
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enable16_counter.eq(enable16_counter - 1),
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If(enable16,
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enable16_counter.eq(self.divisor - 1))
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]
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# TX
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_count16 = Signal(4)
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tx_done = self.tx_ev
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tx_busy = Signal()
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self.sync += [
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tx_done.eq(0),
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If(self.tx_we,
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tx_reg.eq(self.tx_dat),
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tx_bitcount.eq(0),
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tx_count16.eq(1),
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tx_busy.eq(1),
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self.tx.eq(0)
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).Elif(enable16 & tx_busy,
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tx_count16.eq(tx_count16 + 1),
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If(tx_count16 == 0,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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self.tx.eq(1)
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).Elif(tx_bitcount == 9,
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self.tx.eq(1),
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tx_busy.eq(0),
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tx_done.eq(1)
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).Else(
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self.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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)
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]
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# RX
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rx = Signal()
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self.specials += MultiReg(self.rx, rx, "sys")
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rx_r = Signal()
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rx_reg = Signal(8)
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rx_bitcount = Signal(4)
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rx_count16 = Signal(4)
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rx_busy = Signal()
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rx_done = self.rx_ev
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rx_data = self.rx_dat
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self.sync += [
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rx_done.eq(0),
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If(enable16,
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rx_r.eq(rx),
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If(~rx_busy,
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If(~rx & rx_r, # look for start bit
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rx_busy.eq(1),
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rx_count16.eq(7),
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rx_bitcount.eq(0)
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)
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).Else(
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rx_count16.eq(rx_count16 + 1),
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If(rx_count16 == 0,
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rx_bitcount.eq(rx_bitcount + 1),
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If(rx_bitcount == 0,
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If(rx, # verify start bit
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rx_busy.eq(0)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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)
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)
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]
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