litex/migen
Kenneth Ryerson e5e3492afe csr/sram: fix page_bits computation 2013-06-03 21:51:44 +02:00
..
actorlib Make memory ports part of specials 2013-05-28 16:11:34 +02:00
bank New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
bus csr/sram: fix page_bits computation 2013-06-03 21:51:44 +02:00
fhdl bitreverse: fhdl/tools -> genlib/misc 2013-05-30 18:44:37 +02:00
flow New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
genlib genlib/misc: fix import 2013-05-30 18:46:52 +02:00
pytholite Make memory ports part of specials 2013-05-28 16:11:34 +02:00
sim New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00