80 lines
2.6 KiB
Python
80 lines
2.6 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import AutoCSR
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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from milkymist.dvisampler.wer import WER
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from milkymist.dvisampler.decoding import Decoding
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from milkymist.dvisampler.chansync import ChanSync
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from milkymist.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
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from milkymist.dvisampler.dma import DMA
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class DVISampler(Module, AutoCSR):
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def __init__(self, pads, asmiport, n_dma_slots=2):
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self.submodules.edid = EDID(pads)
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self.submodules.clocking = Clocking(pads)
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for datan in range(3):
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name = "data" + str(datan)
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cap = DataCapture(getattr(pads, name + "_p"), getattr(pads, name + "_n"), 8)
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setattr(self.submodules, name + "_cap", cap)
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self.comb += cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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charsync = CharSync()
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setattr(self.submodules, name + "_charsync", charsync)
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self.comb += charsync.raw_data.eq(cap.d)
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wer = WER()
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setattr(self.submodules, name + "_wer", wer)
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self.comb += wer.data.eq(charsync.data)
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decoding = Decoding()
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setattr(self.submodules, name + "_decod", decoding)
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self.comb += [
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decoding.valid_i.eq(charsync.synced),
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decoding.input.eq(charsync.data)
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]
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self.submodules.chansync = ChanSync()
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self.comb += [
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self.chansync.valid_i.eq(self.data0_decod.valid_o & \
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self.data1_decod.valid_o & self.data2_decod.valid_o),
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self.chansync.data_in0.eq(self.data0_decod.output),
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self.chansync.data_in1.eq(self.data1_decod.output),
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self.chansync.data_in2.eq(self.data2_decod.output),
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]
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self.submodules.syncpol = SyncPolarity()
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self.comb += [
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self.syncpol.valid_i.eq(self.chansync.chan_synced),
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self.syncpol.data_in0.eq(self.chansync.data_out0),
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self.syncpol.data_in1.eq(self.chansync.data_out1),
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self.syncpol.data_in2.eq(self.chansync.data_out2)
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]
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self.submodules.resdetection = ResolutionDetection()
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self.comb += [
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self.resdetection.valid_i.eq(self.syncpol.valid_o),
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self.resdetection.de.eq(self.syncpol.de),
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self.resdetection.vsync.eq(self.syncpol.vsync)
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]
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self.submodules.frame = FrameExtraction()
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self.comb += [
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self.frame.valid_i.eq(self.syncpol.valid_o),
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self.frame.de.eq(self.syncpol.de),
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self.frame.vsync.eq(self.syncpol.vsync),
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self.frame.r.eq(self.syncpol.r),
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self.frame.g.eq(self.syncpol.g),
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self.frame.b.eq(self.syncpol.b)
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]
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self.submodules.dma = DMA(asmiport, n_dma_slots)
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self.comb += self.frame.frame.connect(self.dma.frame)
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self.ev = self.dma.ev
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autocsr_exclude = {"ev"}
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