Florent Kermarrec e80cfedd7f gen/genlib/record: fix connect		2016-04-21 12:16:26 +02:00
..
fhdl	gen/sim, fhdl: remove port.we_granularity limitation on simulations	2016-03-23 09:46:54 +01:00
genlib	gen/genlib/record: fix connect	2016-04-21 12:16:26 +02:00
sim	gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)	2016-03-25 13:22:26 +01:00
util	litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented	2015-11-13 14:44:16 +01:00
__init__.py	gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator	2016-03-21 19:15:40 +01:00
MIGEN_LICENSE	litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented	2015-11-13 14:44:16 +01:00