litex/litex/soc
2020-06-16 20:28:57 -04:00
..
cores cpu/mor1kx: fix .data initialization (follow-up to PR #567) 2020-06-16 20:28:57 -04:00
doc soc/doc/csr: allow CSRField.reset to be a Migen Constant. 2020-03-23 18:47:41 +01:00
integration soc_core: Increase sram size default to 8k. 2020-06-15 21:18:26 +02:00
interconnect interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify. 2020-06-01 11:06:23 +02:00
software Merge pull request #565 from gsomlo/gls-cosmetic-spi-fat 2020-06-16 21:49:15 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00