19 lines
474 B
Python
19 lines
474 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from milkymist.dvisampler.edid import EDID
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class DVISampler(Module, AutoReg):
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def __init__(self, inversions=""):
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self.clk = Signal()
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for datan in "012":
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name = "data" + str(datan)
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if datan in inversions:
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name += "_n"
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setattr(self, name, Signal(name=name))
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self.submodules.edid = EDID()
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self.sda = self.edid.sda
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self.scl = self.edid.scl
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