217 lines
5.5 KiB
Python
217 lines
5.5 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.misc import optree
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control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
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class Encoder(Module):
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def __init__(self):
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self.d = Signal(8)
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self.c = Signal(2)
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self.de = Signal()
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self.out = Signal(10)
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###
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# stage 1 - count number of 1s in data
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d = Signal(8)
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n1d = Signal(max=9)
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self.sync += [
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n1d.eq(optree("+", [self.d[i] for i in range(8)])),
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d.eq(self.d)
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]
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# stage 2 - add 9th bit
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q_m = Signal(9)
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q_m8_n = Signal()
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self.comb += q_m8_n.eq((n1d > 4) | ((n1d == 4) & ~d[0]))
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for i in range(8):
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if i:
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curval = curval ^ d[i] ^ q_m8_n
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else:
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curval = d[0]
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self.sync += q_m[i].eq(curval)
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self.sync += q_m[8].eq(~q_m8_n)
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# stage 3 - count number of 1s and 0s in q_m[:8]
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q_m_r = Signal(9)
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n0q_m = Signal(max=9)
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n1q_m = Signal(max=9)
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self.sync += [
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n0q_m.eq(optree("+", [~q_m[i] for i in range(8)])),
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n1q_m.eq(optree("+", [q_m[i] for i in range(8)])),
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q_m_r.eq(q_m)
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]
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# stage 4 - final encoding
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cnt = Signal((6, True))
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s_c = self.c
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s_de = self.de
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for p in range(3):
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new_c = Signal(2)
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new_de = Signal()
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self.sync += new_c.eq(s_c), new_de.eq(s_de)
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s_c, s_de = new_c, new_de
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self.sync += If(s_de,
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If((cnt == 0) | (n1q_m == n0q_m),
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self.out[9].eq(~q_m_r[8]),
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self.out[8].eq(q_m_r[8]),
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If(q_m_r[8],
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self.out[:8].eq(q_m_r[:8]),
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cnt.eq(cnt + n1q_m - n0q_m)
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).Else(
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self.out[:8].eq(~q_m_r[:8]),
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cnt.eq(cnt + n0q_m - n1q_m)
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)
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).Else(
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If((~cnt[5] & (n1q_m > n0q_m)) | (cnt[5] & (n0q_m > n1q_m)),
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self.out[9].eq(1),
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self.out[8].eq(q_m_r[8]),
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self.out[:8].eq(~q_m_r[:8]),
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cnt.eq(cnt + Cat(0, q_m_r[8]) + n0q_m - n1q_m)
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).Else(
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self.out[9].eq(0),
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self.out[8].eq(q_m_r[8]),
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self.out[:8].eq(q_m_r[:8]),
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cnt.eq(cnt - Cat(0, ~q_m_r[8]) + n1q_m - n0q_m)
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)
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)
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).Else(
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self.out.eq(Array(control_tokens)[s_c]),
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cnt.eq(0)
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)
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class _EncoderSerializer(Module):
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def __init__(self, serdesstrobe, pad_p, pad_n):
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self.submodules.encoder = RenameClockDomains(Encoder(), "pix")
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self.d, self.c, self.de = self.encoder.d, self.encoder.c, self.encoder.de
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###
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# 2X soft serialization
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ed_2x = Signal(5)
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self.sync.pix2x += ed_2x.eq(Mux(ClockSignal("pix"), self.encoder.out[:5], self.encoder.out[5:]))
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# 5X hard serialization
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cascade_di = Signal()
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cascade_do = Signal()
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cascade_ti = Signal()
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cascade_to = Signal()
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pad_se = Signal()
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self.specials += [
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Instance("OSERDES2",
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p_DATA_WIDTH=5, p_DATA_RATE_OQ="SDR", p_DATA_RATE_OT="SDR",
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p_SERDES_MODE="MASTER", p_OUTPUT_MODE="DIFFERENTIAL",
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o_OQ=pad_se,
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i_OCE=1, i_IOCE=serdesstrobe, i_RST=0,
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i_CLK0=ClockSignal("pix10x"), i_CLK1=0, i_CLKDIV=ClockSignal("pix2x"),
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i_D1=ed_2x[4], i_D2=0, i_D3=0, i_D4=0,
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i_T1=0, i_T2=0, i_T3=0, i_T4=0,
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i_TRAIN=0, i_TCE=1,
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i_SHIFTIN1=1, i_SHIFTIN2=1,
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i_SHIFTIN3=cascade_do, i_SHIFTIN4=cascade_to,
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o_SHIFTOUT1=cascade_di, o_SHIFTOUT2=cascade_ti),
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Instance("OSERDES2",
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p_DATA_WIDTH=5, p_DATA_RATE_OQ="SDR", p_DATA_RATE_OT="SDR",
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p_SERDES_MODE="SLAVE", p_OUTPUT_MODE="DIFFERENTIAL",
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i_OCE=1, i_IOCE=serdesstrobe, i_RST=0,
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i_CLK0=ClockSignal("pix10x"), i_CLK1=0, i_CLKDIV=ClockSignal("pix2x"),
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i_D1=ed_2x[0], i_D2=ed_2x[1], i_D3=ed_2x[2], i_D4=ed_2x[3],
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i_T1=0, i_T2=0, i_T3=0, i_T4=0,
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i_TRAIN=0, i_TCE=1,
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i_SHIFTIN1=cascade_di, i_SHIFTIN2=cascade_ti,
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i_SHIFTIN3=1, i_SHIFTIN4=1,
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o_SHIFTOUT3=cascade_do, o_SHIFTOUT4=cascade_to),
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Instance("OBUFDS", i_I=pad_se, o_O=pad_p, o_OB=pad_n)
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]
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class PHY(Module):
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def __init__(self, serdesstrobe, pads):
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self.hsync = Signal()
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self.vsync = Signal()
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self.de = Signal()
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self.r = Signal(8)
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self.g = Signal(8)
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self.b = Signal(8)
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###
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self.submodules.es0 = _EncoderSerializer(serdesstrobe, pads.data0_p, pads.data0_n)
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self.submodules.es1 = _EncoderSerializer(serdesstrobe, pads.data1_p, pads.data1_n)
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self.submodules.es2 = _EncoderSerializer(serdesstrobe, pads.data2_p, pads.data2_n)
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self.comb += [
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self.es0.c.eq(Cat(self.hsync, self.vsync)),
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self.es1.c.eq(0),
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self.es2.c.eq(0),
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self.es0.de.eq(self.de),
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self.es1.de.eq(self.de),
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self.es2.de.eq(self.de),
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]
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class _EncoderTB(Module):
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def __init__(self, inputs):
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self.outs = []
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self._iter_inputs = iter(inputs)
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self._end_cycle = None
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self.submodules.dut = Encoder()
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self.comb += self.dut.de.eq(1)
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def do_simulation(self, s):
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if self._end_cycle is None:
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try:
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nv = next(self._iter_inputs)
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except StopIteration:
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self._end_cycle = s.cycle_counter + 4
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else:
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s.wr(self.dut.d, nv)
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if s.cycle_counter == self._end_cycle:
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s.interrupt = True
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if s.cycle_counter > 4:
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self.outs.append(s.rd(self.dut.out))
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def _bit(i, n):
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return (i >> n) & 1
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def _decode_tmds(b):
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try:
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c = control_tokens.index(b)
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de = False
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except ValueError:
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c = 0
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de = True
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vsync = bool(c & 2)
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hsync = bool(c & 1)
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value = _bit(b, 0) ^ _bit(b, 9)
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for i in range(1, 8):
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value |= (_bit(b, i) ^ _bit(b, i-1) ^ (~_bit(b, 8) & 1)) << i
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return de, hsync, vsync, value
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if __name__ == "__main__":
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from migen.sim.generic import Simulator
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from random import Random
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rng = Random(788)
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test_list = [rng.randrange(256) for i in range(500)]
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tb = _EncoderTB(test_list)
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Simulator(tb).run()
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check = [_decode_tmds(out)[3] for out in tb.outs]
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assert(check == test_list)
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nb0 = 0
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nb1 = 0
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for out in tb.outs:
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for i in range(10):
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if _bit(out, i):
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nb1 += 1
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else:
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nb0 += 1
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print("0/1: {}/{} ({:.2f})".format(nb0, nb1, nb0/nb1))
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