246 lines
6.5 KiB
Python
246 lines
6.5 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
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from migen.genlib.record import layout_len, Record
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def _inc(signal, modulo):
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if modulo == 2**flen(signal):
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return signal.eq(signal + 1)
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else:
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return If(signal == (modulo - 1),
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signal.eq(0)
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).Else(
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signal.eq(signal + 1)
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)
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class _FIFOInterface:
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"""
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Data written to the input interface (`din`, `we`, `writable`) is
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buffered and can be read at the output interface (`dout`, `re`,
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`readable`). The data entry written first to the input
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also appears first on the output.
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Parameters
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----------
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width_or_layout : int, layout
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Bit width or `Record` layout for the data.
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depth : int
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Depth of the FIFO.
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Attributes
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----------
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din : in, width_or_layout
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Input data either flat or Record structured.
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writable : out
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There is space in the FIFO and `we` can be asserted to load new data.
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we : in
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Write enable signal to latch `din` into the FIFO. Does nothing if
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`writable` is not asserted.
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dout : out, width_or_layout
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Output data, same type as `din`. Only valid if `readable` is
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asserted.
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readable : out
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Output data `dout` valid, FIFO not empty.
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re : in
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Acknowledge `dout`. If asserted, the next entry will be
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available on the next cycle (if `readable` is high then).
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"""
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def __init__(self, width_or_layout, depth):
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self.we = Signal()
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self.writable = Signal() # not full
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self.re = Signal()
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self.readable = Signal() # not empty
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if isinstance(width_or_layout, list):
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self.din = Record(width_or_layout)
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self.dout = Record(width_or_layout)
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self.din_bits = self.din.raw_bits()
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self.dout_bits = self.dout.raw_bits()
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self.width = layout_len(width_or_layout)
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else:
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self.din = Signal(width_or_layout)
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self.dout = Signal(width_or_layout)
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self.din_bits = self.din
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self.dout_bits = self.dout
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self.width = width_or_layout
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class SyncFIFO(Module, _FIFOInterface):
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"""Synchronous FIFO (first in, first out)
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Read and write interfaces are accessed from the same clock domain.
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If different clock domains are needed, use :class:`AsyncFIFO`.
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{interface}
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level : out
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Number of unread entries.
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flush : in
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Flush the FIFO discarding pending write.
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In the next cycle `readable` will be deasserted
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and `writable` will be asserted, `level` will be zero.
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"""
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__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
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def __init__(self, width_or_layout, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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self.flush = Signal()
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self.level = Signal(max=depth+1)
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###
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do_write = Signal()
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do_read = Signal()
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self.comb += [
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do_write.eq(self.writable & self.we),
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do_read.eq(self.readable & self.re)
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]
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produce = Signal(max=depth)
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consume = Signal(max=depth)
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storage = Memory(self.width, depth)
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self.specials += storage
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wrport = storage.get_port(write_capable=True)
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self.specials += wrport
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self.comb += [
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wrport.adr.eq(produce),
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wrport.dat_w.eq(self.din_bits),
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wrport.we.eq(do_write)
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]
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self.sync += If(do_write, _inc(produce, depth))
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rdport = storage.get_port(async_read=True)
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self.specials += rdport
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self.comb += [
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rdport.adr.eq(consume),
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self.dout_bits.eq(rdport.dat_r)
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]
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self.sync += If(do_read, _inc(consume, depth))
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self.sync += [
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If(self.flush,
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produce.eq(0),
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consume.eq(0),
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self.level.eq(0),
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).Elif(do_write,
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If(~do_read, self.level.eq(self.level + 1))
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).Elif(do_read,
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self.level.eq(self.level - 1)
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)
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]
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self.comb += [
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self.writable.eq(self.level != depth),
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self.readable.eq(self.level != 0)
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]
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class SyncFIFOClassic(Module, _FIFOInterface):
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def __init__(self, width_or_layout, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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self.submodules.fifo = fifo = SyncFIFO(width_or_layout, depth)
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self.writable = fifo.writable
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self.din_bits = fifo.din_bits
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self.din = fifo.din
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self.we = fifo.we
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self.readable = fifo.readable
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self.re = fifo.re
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self.flush = fifo.flush
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self.level = fifo.level
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###
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self.sync += [
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If(self.re & self.readable,
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self.dout_bits.eq(fifo.dout_bits),
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)]
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class SyncFIFOBuffered(Module, _FIFOInterface):
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def __init__(self, width_or_layout, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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self.submodules.fifo = fifo = SyncFIFOClassic(width_or_layout, depth)
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self.writable = fifo.writable
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self.din_bits = fifo.din_bits
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self.din = fifo.din
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self.we = fifo.we
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self.dout_bits = fifo.dout_bits
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self.dout = fifo.dout
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self.flush = fifo.flush
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self.level = fifo.level
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###
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self.comb += [
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fifo.re.eq(fifo.readable & (~self.readable | self.re)),
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]
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self.sync += [
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If(self.flush,
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self.readable.eq(0),
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).Elif(fifo.re,
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self.readable.eq(1),
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).Elif(self.re,
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self.readable.eq(0),
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)]
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class AsyncFIFO(Module, _FIFOInterface):
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"""Asynchronous FIFO (first in, first out)
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Read and write interfaces are accessed from different clock domains,
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named `read` and `write`. Use `RenameClockDomains` to rename to
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other names.
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{interface}
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"""
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__doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
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def __init__(self, width_or_layout, depth):
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_FIFOInterface.__init__(self, width_or_layout, depth)
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###
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depth_bits = log2_int(depth, True)
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produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
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consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
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self.submodules += produce, consume
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self.comb += [
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produce.ce.eq(self.writable & self.we),
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consume.ce.eq(self.readable & self.re)
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]
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produce_rdomain = Signal(depth_bits+1)
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self.specials += [
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NoRetiming(produce.q),
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MultiReg(produce.q, produce_rdomain, "read")
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]
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consume_wdomain = Signal(depth_bits+1)
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self.specials += [
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NoRetiming(consume.q),
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MultiReg(consume.q, consume_wdomain, "write")
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]
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if depth_bits == 1:
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self.comb += self.writable.eq((produce.q[-1] == consume_wdomain[-1])
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| (produce.q[-2] == consume_wdomain[-2]))
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else:
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self.comb += [
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self.writable.eq((produce.q[-1] == consume_wdomain[-1])
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| (produce.q[-2] == consume_wdomain[-2])
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| (produce.q[:-2] != consume_wdomain[:-2]))
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]
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self.comb += self.readable.eq(consume.q != produce_rdomain)
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storage = Memory(self.width, depth)
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self.specials += storage
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wrport = storage.get_port(write_capable=True, clock_domain="write")
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self.specials += wrport
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self.comb += [
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wrport.adr.eq(produce.q_binary[:-1]),
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wrport.dat_w.eq(self.din_bits),
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wrport.we.eq(produce.ce)
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]
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rdport = storage.get_port(clock_domain="read")
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self.specials += rdport
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self.comb += [
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rdport.adr.eq(consume.q_next_binary[:-1]),
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self.dout_bits.eq(rdport.dat_r)
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]
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