363 lines
9.9 KiB
Python
363 lines
9.9 KiB
Python
# 1:2 frequency-ratio DDR / LPDDR / DDR2 PHY for
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# Spartan-6
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#
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# Assert dfi_wrdata_en and present the data
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# on dfi_wrdata_mask/dfi_wrdata in the same
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# cycle as the write command.
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#
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# Assert dfi_rddata_en in the same cycle as the read
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# command. The data will come back on dfi_rddata
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# 5 cycles later, along with the assertion
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# of dfi_rddata_valid.
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#
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# This PHY only supports CAS Latency 3.
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# Read commands must be sent on phase 0.
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# Write commands must be sent on phase 1.
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#
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# Todo:
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# - use CSR for bitslip?
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# - add configurable CAS Latency
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# - automatically determines wrphase / rdphase / latencies
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from migen.fhdl.std import *
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from migen.bus.dfi import *
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from migen.genlib.record import *
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from milkymist import lasmicon
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class S6DDRPHY(Module):
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def __init__(self, pads, memtype, nphases, cl, bitslip):
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if memtype not in ["DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
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if cl != 3:
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raise NotImplementedError("S6DDRPHY only supports CAS LATENCY 3")
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a = flen(pads.a)
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ba = flen(pads.ba)
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d = flen(pads.dq)
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self.phy_settings = lasmicon.PhySettings(
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memtype=memtype,
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dfi_d=2*d,
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nphases=nphases,
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rdphase=0,
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wrphase=1,
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cl=cl,
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read_latency=5,
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write_latency=0
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)
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self.dfi = Interface(a, ba, nphases*d, nphases)
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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###
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# sys_clk : system clk, used for dfi interface
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# sdram_half_clk : half rate sdram clk
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# sdram_full_wr_clk : full rate sdram write clk
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# sdram_full_rd_clk : full rate sdram write clk
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sd_sys = getattr(self.sync, "sys")
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sd_sdram_half = getattr(self.sync, "sdram_half")
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sys_clk = ClockSignal("sys")
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sdram_half_clk = ClockSignal("sdram_half")
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sdram_full_wr_clk = ClockSignal("sdram_full_wr")
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sdram_full_rd_clk = ClockSignal("sdram_full_rd")
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#
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# Command/address
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#
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# select active phase
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# sys_clk ----____----____
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# phase_sel(nphases=1) 0 0
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# phase_sel(nphases=2) 0 1 0 1
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# phase_sel(nphases=4) 0 1 2 3 0 1 2 3
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phase_sel = Signal(log2_int(nphases))
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sys_clk_d = Signal()
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sd_sdram_half += [
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If(sys_clk & ~sys_clk_d, phase_sel.eq(0)
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).Else(phase_sel.eq(phase_sel+1)),
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sys_clk_d.eq(sys_clk)
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]
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# register dfi cmds on half_rate clk
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r_dfi = Array(Record(phase_cmd_description(a, ba)) for i in range(nphases))
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for n, phase in enumerate(self.dfi.phases):
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sd_sdram_half +=[
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r_dfi[n].address.eq(phase.address),
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r_dfi[n].bank.eq(phase.bank),
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r_dfi[n].cs_n.eq(phase.cs_n),
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r_dfi[n].cke.eq(phase.cke),
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r_dfi[n].cas_n.eq(phase.cas_n),
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r_dfi[n].ras_n.eq(phase.ras_n),
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r_dfi[n].we_n.eq(phase.we_n)
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]
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# output cmds
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sd_sdram_half += [
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pads.a.eq(r_dfi[phase_sel].address),
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pads.ba.eq(r_dfi[phase_sel].bank),
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pads.cs_n.eq(r_dfi[phase_sel].cs_n),
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pads.cke.eq(r_dfi[phase_sel].cke),
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pads.ras_n.eq(r_dfi[phase_sel].ras_n),
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pads.cas_n.eq(r_dfi[phase_sel].cas_n),
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pads.we_n.eq(r_dfi[phase_sel].we_n)
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]
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#
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# Bitslip
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#
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bitslip_cnt = Signal(4)
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bitslip_inc = Signal()
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sd_sys += [
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If(bitslip_cnt == bitslip,
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bitslip_inc.eq(0)
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).Else(
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bitslip_cnt.eq(bitslip_cnt+1),
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bitslip_inc.eq(1)
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)
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]
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#
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# DQ/DQS/DM data
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#
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sdram_half_clk_n = Signal()
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self.comb += sdram_half_clk_n.eq(~sdram_half_clk)
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postamble = Signal()
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drive_dqs = Signal()
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dqs_t_d0 = Signal()
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dqs_t_d1 = Signal()
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dqs_o = Signal(d//8)
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dqs_t = Signal(d//8)
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self.comb += [
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dqs_t_d0.eq(~(drive_dqs | postamble)),
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dqs_t_d1.eq(~drive_dqs),
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]
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for i in range(d//8):
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# DQS output
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self.specials += Instance("ODDR2",
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Instance.Parameter("DDR_ALIGNMENT", "C1"),
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Instance.Parameter("INIT", 0),
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Instance.Parameter("SRTYPE", "ASYNC"),
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Instance.Input("C0", sdram_half_clk),
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Instance.Input("C1", sdram_half_clk_n),
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Instance.Input("CE", 1),
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Instance.Input("D0", 0),
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Instance.Input("D1", 1),
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Instance.Input("R", 0),
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Instance.Input("S", 0),
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Instance.Output("Q", dqs_o[i])
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)
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# DQS tristate cmd
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self.specials += Instance("ODDR2",
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Instance.Parameter("DDR_ALIGNMENT", "C1"),
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Instance.Parameter("INIT", 0),
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Instance.Parameter("SRTYPE", "ASYNC"),
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Instance.Input("C0", sdram_half_clk),
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Instance.Input("C1", sdram_half_clk_n),
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Instance.Input("CE", 1),
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Instance.Input("D0", dqs_t_d0),
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Instance.Input("D1", dqs_t_d1),
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Instance.Input("R", 0),
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Instance.Input("S", 0),
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Instance.Output("Q", dqs_t[i])
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)
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# DQS tristate buffer
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self.specials += Instance("OBUFT",
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Instance.Input("I", dqs_o[i]),
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Instance.Input("T", dqs_t[i]),
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Instance.Output("O", pads.dqs[i])
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)
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sd_sdram_half += postamble.eq(drive_dqs)
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d_dfi = [Record(phase_wrdata_description(nphases*d)+phase_rddata_description(nphases*d))
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for i in range(2*nphases)]
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for n, phase in enumerate(self.dfi.phases):
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self.comb += [
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d_dfi[n].wrdata.eq(phase.wrdata),
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d_dfi[n].wrdata_mask.eq(phase.wrdata_mask),
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d_dfi[n].wrdata_en.eq(phase.wrdata_en),
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d_dfi[n].rddata_en.eq(phase.rddata_en),
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]
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sd_sys += [
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d_dfi[nphases+n].wrdata.eq(phase.wrdata),
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d_dfi[nphases+n].wrdata_mask.eq(phase.wrdata_mask)
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]
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drive_dq = Signal()
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drive_dq_n = Signal()
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d_drive_dq = Signal()
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d_drive_dq_n = Signal()
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self.comb += [
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drive_dq_n.eq(~drive_dq),
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d_drive_dq_n.eq(~d_drive_dq)
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]
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dq_t = Signal(d)
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dq_o = Signal(d)
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dq_i = Signal(d)
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for i in range(d):
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# Data serializer
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self.specials += Instance("OSERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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Instance.Parameter("DATA_RATE_OQ", "SDR"),
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Instance.Parameter("DATA_RATE_OT", "SDR"),
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Instance.Parameter("SERDES_MODE", "NONE"),
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Instance.Parameter("OUTPUT_MODE", "SINGLE_ENDED"),
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Instance.Output("OQ", dq_o[i]),
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Instance.Input("OCE", 1),
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Instance.Input("CLK0", sdram_full_wr_clk),
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Instance.Input("CLK1", 0),
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Instance.Input("IOCE", self.clk4x_wr_strb),
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Instance.Input("RST", 0),
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Instance.Input("CLKDIV", sys_clk),
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Instance.Input("D1", d_dfi[1*nphases+0].wrdata[i]),
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Instance.Input("D2", d_dfi[1*nphases+1].wrdata[i+d]),
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Instance.Input("D3", d_dfi[1*nphases+1].wrdata[i]),
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Instance.Input("D4", d_dfi[0*nphases+0].wrdata[i+d]),
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Instance.Output("TQ", dq_t[i]),
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Instance.Input("T1", d_drive_dq_n),
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Instance.Input("T2", d_drive_dq_n),
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Instance.Input("T3", d_drive_dq_n),
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Instance.Input("T4", drive_dq_n),
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Instance.Input("TRAIN", 0),
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Instance.Input("TCE", 1),
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Instance.Input("SHIFTIN1", 0),
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Instance.Input("SHIFTIN2", 0),
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Instance.Input("SHIFTIN3", 0),
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Instance.Input("SHIFTIN4", 0),
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Instance.Output("SHIFTOUT1"),
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Instance.Output("SHIFTOUT2"),
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Instance.Output("SHIFTOUT3"),
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Instance.Output("SHIFTOUT4"),
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)
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# Data deserializer
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self.specials += Instance("ISERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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Instance.Parameter("DATA_RATE", "SDR"),
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Instance.Parameter("BITSLIP_ENABLE", "TRUE"),
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Instance.Parameter("SERDES_MODE", "NONE"),
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Instance.Parameter("INTERFACE_TYPE", "RETIMED"),
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Instance.Input("D", dq_i[i]),
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Instance.Input("CE0", 1),
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Instance.Input("CLK0", sdram_full_rd_clk),
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Instance.Input("CLK1", 0),
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Instance.Input("IOCE", self.clk4x_rd_strb),
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Instance.Input("RST", ResetSignal()),
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Instance.Input("CLKDIV", sys_clk),
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Instance.Output("SHIFTIN"),
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Instance.Input("BITSLIP", bitslip_inc),
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Instance.Output("FABRICOUT"),
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Instance.Output("Q1", d_dfi[0*nphases+0].rddata[i+d]),
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Instance.Output("Q2", d_dfi[0*nphases+0].rddata[i]),
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Instance.Output("Q3", d_dfi[0*nphases+1].rddata[i+d]),
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Instance.Output("Q4", d_dfi[0*nphases+1].rddata[i]),
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Instance.Output("DFB"),
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Instance.Output("CFB0"),
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Instance.Output("CFB1"),
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Instance.Output("VALID"),
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Instance.Output("INCDEC"),
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Instance.Output("SHIFTOUT")
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)
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# Data buffer
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self.specials += Instance("IOBUF",
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Instance.Input("I", dq_o[i]),
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Instance.Output("O", dq_i[i]),
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Instance.Input("T", dq_t[i]),
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Instance.InOut("IO", pads.dq[i])
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)
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for i in range(d//8):
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# Mask serializer
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self.specials += Instance("OSERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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Instance.Parameter("DATA_RATE_OQ", "SDR"),
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Instance.Parameter("DATA_RATE_OT", "SDR"),
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Instance.Parameter("SERDES_MODE", "NONE"),
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Instance.Parameter("OUTPUT_MODE", "SINGLE_ENDED"),
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Instance.Output("OQ", pads.dm[i]),
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Instance.Input("OCE", 1),
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Instance.Input("CLK0", sdram_full_wr_clk),
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Instance.Input("CLK1", 0),
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Instance.Input("IOCE", self.clk4x_wr_strb),
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Instance.Input("RST", 0),
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Instance.Input("CLKDIV", sys_clk),
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Instance.Input("D1", d_dfi[1*nphases+0].wrdata_mask[i]),
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Instance.Input("D2", d_dfi[1*nphases+1].wrdata_mask[i+d//8]),
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Instance.Input("D3", d_dfi[1*nphases+1].wrdata_mask[i]),
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Instance.Input("D4", d_dfi[0*nphases+0].wrdata_mask[i+d//8]),
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Instance.Output("TQ"),
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Instance.Input("T1"),
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Instance.Input("T2"),
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Instance.Input("T3"),
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Instance.Input("T4"),
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Instance.Input("TRAIN", 0),
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Instance.Input("TCE", 0),
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Instance.Input("SHIFTIN1", 0),
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Instance.Input("SHIFTIN2", 0),
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Instance.Input("SHIFTIN3", 0),
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Instance.Input("SHIFTIN4", 0),
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Instance.Output("SHIFTOUT1"),
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Instance.Output("SHIFTOUT2"),
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Instance.Output("SHIFTOUT3"),
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Instance.Output("SHIFTOUT4"),
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)
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#
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# DQ/DQS/DM control
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#
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self.comb += drive_dq.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
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sd_sys += d_drive_dq.eq(drive_dq)
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d_dfi_wrdata_en = Signal()
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sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
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r_dfi_wrdata_en = Signal(2)
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sd_sdram_half += r_dfi_wrdata_en.eq(Cat(d_dfi_wrdata_en, r_dfi_wrdata_en[0]))
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self.comb += drive_dqs.eq(r_dfi_wrdata_en[1])
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rddata_sr = Signal(self.phy_settings.read_latency)
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sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.phy_settings.read_latency],
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d_dfi[self.phy_settings.rdphase].rddata_en))
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for n, phase in enumerate(self.dfi.phases):
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self.comb += [
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phase.rddata.eq(d_dfi[n].rddata),
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phase.rddata_valid.eq(rddata_sr[0]),
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]
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