Florent Kermarrec ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" ... This probably breaks simulation with Icarus Verilog (and others simulators?)		2015-03-18 14:59:22 +01:00
..
__init__.py	…
bitcontainer.py	migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)	2013-12-10 23:32:12 +01:00
decorators.py	…
edif.py	…
module.py	…
namer.py	…
simplify.py	…
specials.py	…
std.py	…
structure.py	…
tools.py	…
tracer.py	…
verilog.py	…
visit.py	…