litex/litex/soc
2019-05-13 10:59:26 +02:00
..
cores cpu/vexriscv/core: update 2019-05-13 10:59:26 +02:00
integration soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy 2019-05-10 15:46:22 +02:00
interconnect soc/interconnect: remove axi_lite 2019-05-11 09:12:20 +02:00
software LICENSE: clarify 2019-05-11 09:26:51 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00