234 lines
6.2 KiB
Python
234 lines
6.2 KiB
Python
from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migen.corelogic.misc import optree
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class Storage:
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#
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# Definition
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#
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def __init__(self, width, depth):
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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#Control
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self.rst = Signal()
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self.start = Signal()
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self.offset = Signal(BV(self.depth_width))
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self.size = Signal(BV(self.depth_width))
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self.done = Signal()
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self.run = Signal()
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#Write Path
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self.put = Signal()
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self.put_dat = Signal(BV(self.width))
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self._put_ptr = Signal(BV(self.depth_width))
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self._put_ptr_stop = Signal(BV(self.depth_width))
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self._put_port = MemoryPort(adr=self._put_ptr, we=self.put, dat_w=self.put_dat)
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#Read Path
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self.get = Signal()
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self.get_dat = Signal(BV(self.width))
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self._get_ptr = Signal(BV(self.depth_width))
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self._get_port = MemoryPort(adr=self._get_ptr, re=self.get, dat_r=self.get_dat)
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#Others
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self._mem = Memory(self.width, self.depth, self._put_port, self._get_port)
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def get_fragment(self):
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comb = []
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sync = []
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memories = [self._mem]
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size_minus_offset = Signal(BV(self.depth_width))
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comb += [size_minus_offset.eq(self.size-self.offset)]
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#Control
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sync += [
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If(self.rst,
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self.run.eq(0),
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self._put_ptr.eq(0)
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).Elif(self.start & ~self.run,
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self.run.eq(1),
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self._put_ptr_stop.eq(self._put_ptr + self.size - self.offset)
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).Elif(self.done,
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self.run.eq(0)
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),
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If(self.put & ~self.done,
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self._put_ptr.eq(self._put_ptr+1)
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),
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If(self.rst,
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self.done.eq(0)
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).Elif((self._put_ptr == self._put_ptr_stop) & self.run,
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self.done.eq(1)
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),
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If(self.rst,
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self._get_ptr.eq(0)
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).Elif(self.start & ~self.run,
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self._get_ptr.eq(self._put_ptr-self.offset-1)
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).Elif(self.get,
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self._get_ptr.eq(self._get_ptr+1)
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)
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]
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return Fragment(comb=comb, sync=sync, memories=memories)
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class Sequencer:
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#
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# Definition
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#
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def __init__(self,depth):
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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# Controller interface
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self.ctl_rst = Signal()
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self.ctl_offset = Signal(BV(self.depth_width))
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self.ctl_size = Signal(BV(self.depth_width))
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self.ctl_arm = Signal()
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self.ctl_done = Signal()
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self._ctl_arm_d = Signal()
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# Triggers interface
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self.trig_hit = Signal()
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self._trig_hit_d = Signal()
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# Recorder interface
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self.rec_offset = Signal(BV(self.depth_width))
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self.rec_size = Signal(BV(self.depth_width))
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self.rec_start = Signal()
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self.rec_done = Signal()
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# Others
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self.enable = Signal()
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def get_fragment(self):
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comb = []
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sync = []
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#Control
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sync += [
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If(self.ctl_rst,
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self.enable.eq(0)
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).Elif(self.ctl_arm & ~self._ctl_arm_d,
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self.enable.eq(1)
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).Elif(self.rec_done,
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self.enable.eq(0)
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),
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self._ctl_arm_d.eq(self.ctl_arm)
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]
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sync += [self._trig_hit_d.eq(self.trig_hit)]
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comb += [
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self.rec_offset.eq(self.ctl_offset),
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self.rec_size.eq(self.ctl_size),
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self.rec_start.eq(self.enable & (self.trig_hit & ~self._trig_hit_d)),
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self.ctl_done.eq(~self.enable)
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]
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return Fragment(comb=comb, sync=sync)
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class Recorder:
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#
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# Definition
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#
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def __init__(self, width, depth, address = 0x0000, interface = None):
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self.address = address
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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self.interface = interface
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self.storage = Storage(self.width, self.depth)
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self.sequencer = Sequencer(self.depth)
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# Csr interface
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self._rst = RegisterField("rst", reset=1)
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self._arm = RegisterField("arm", reset=0)
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self._done = RegisterField("done", reset=0, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._size = RegisterField("size", self.depth_width, reset=1)
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self._offset = RegisterField("offset", self.depth_width, reset=1)
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self._get = RegisterField("get", reset=0)
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self._get_dat = RegisterField("get_dat", self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self.regs = [self._rst, self._arm, self._done,
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self._size, self._offset,
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self._get, self._get_dat]
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self.bank = csrgen.Bank(self.regs,address=self.address)
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# Trigger Interface
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self.trig_hit = Signal()
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self.trig_dat = Signal(BV(self.width))
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def set_address(self, address):
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self.address = address
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self.bank = csrgen.Bank(self.regs,address=self.address)
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def set_interface(self, interface):
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self.interface = interface
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def get_fragment(self):
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comb = []
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sync = []
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_get_d = Signal()
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_get_rising = Signal()
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sync += [
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_get_d.eq(self._get.field.r),
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_get_rising.eq(self._get.field.r & ~_get_d)
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]
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#Bank <--> Storage / Sequencer
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comb += [
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self.sequencer.ctl_rst.eq(self._rst.field.r),
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self.storage.rst.eq(self._rst.field.r),
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self.sequencer.ctl_offset.eq(self._offset.field.r),
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self.sequencer.ctl_size.eq(self._size.field.r),
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self.sequencer.ctl_arm.eq(self._arm.field.r),
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self._done.field.w.eq(self.sequencer.ctl_done),
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self.storage.get.eq(_get_rising),
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self._get_dat.field.w.eq(self.storage.get_dat)
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]
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#Storage <--> Sequencer <--> Trigger
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comb += [
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self.storage.offset.eq(self.sequencer.rec_offset),
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self.storage.size.eq(self.sequencer.rec_size),
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self.storage.start.eq(self.sequencer.rec_start),
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self.sequencer.rec_done.eq(self.storage.done),
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self.sequencer.trig_hit.eq(self.trig_hit),
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self.storage.put.eq(self.sequencer.enable),
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self.storage.put_dat.eq(self.trig_dat)
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]
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return self.bank.get_fragment()+\
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self.storage.get_fragment()+self.sequencer.get_fragment()+\
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Fragment(comb=comb, sync=sync)
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#
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#Driver
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#
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def reset(self):
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self.interface.write(self.address + 0x00, 1)
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self.interface.write(self.address + 0x00, 0)
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def arm(self):
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self.interface.write(self.address + 0x01, 1)
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self.interface.write(self.address + 0x01, 0)
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def is_done(self):
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return self.interface.read(self.address + 0x02) == 1
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def size(self, dat):
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self.size = dat
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self.interface.write_n(self.address + 0x03, dat, 16)
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def offset(self, dat):
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self.interface.write_n(self.address + 0x05, dat, 16)
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def read(self, size):
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r = []
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for i in range(size):
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self.interface.write(self.address+7, 1)
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self.interface.write(self.address+7, 0)
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r.append(self.interface.read_n(self.address+8,self.width))
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return r
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