24 lines
561 B
Python
24 lines
561 B
Python
from migen.fhdl.structure import *
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from migen.transform.unroll import unroll_sync
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from migen.fhdl import verilog
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x = Signal(BV(4))
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y = Signal(BV(4))
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acc = Signal(BV(4), variable=True)
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z = Signal()
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sync = [
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If(acc == 2, acc.eq(3)),
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acc.eq(acc + x + y),
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z.eq(acc == 0)
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]
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n = 5
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xs = [Signal(BV(4)) for i in range(n)]
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ys = [Signal(BV(4)) for i in range(n)]
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accs = [Signal(BV(4)) for i in range(n)]
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zs = [Signal() for i in range(n)]
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sync_u = unroll_sync(sync, {x: xs, y: ys, acc: accs, z: zs})
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print(verilog.convert(Fragment(sync=sync_u), ios=set(xs+ys+zs)))
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