61 lines
1.8 KiB
Python
61 lines
1.8 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Instance
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from migen.bus import wishbone
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from migen.fhdl import verilog
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class LM32:
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def __init__(self):
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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self.interrupt = Signal(32)
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self.ext_break = Signal()
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self._i_adr_o = Signal(32)
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self._d_adr_o = Signal(32)
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self._inst = Instance("lm32_top",
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Instance.ClockPort("clk_i"),
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Instance.ResetPort("rst_i"),
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Instance.Input("interrupt", self.interrupt),
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#Instance.Input("ext_break", self.ext_break),
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Instance.Output("I_ADR_O", self._i_adr_o),
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Instance.Output("I_DAT_O", i.dat_w),
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Instance.Output("I_SEL_O", i.sel),
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Instance.Output("I_CYC_O", i.cyc),
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Instance.Output("I_STB_O", i.stb),
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Instance.Output("I_WE_O", i.we),
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Instance.Output("I_CTI_O", i.cti),
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Instance.Output("I_LOCK_O"),
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Instance.Output("I_BTE_O", i.bte),
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Instance.Input("I_DAT_I", i.dat_r),
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Instance.Input("I_ACK_I", i.ack),
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Instance.Input("I_ERR_I", i.err),
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Instance.Input("I_RTY_I", 0),
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Instance.Output("D_ADR_O", self._d_adr_o),
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Instance.Output("D_DAT_O", d.dat_w),
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Instance.Output("D_SEL_O", d.sel),
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Instance.Output("D_CYC_O", d.cyc),
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Instance.Output("D_STB_O", d.stb),
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Instance.Output("D_WE_O", d.we),
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Instance.Output("D_CTI_O", d.cti),
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Instance.Output("D_LOCK_O"),
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Instance.Output("D_BTE_O", d.bte),
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Instance.Input("D_DAT_I", d.dat_r),
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Instance.Input("D_ACK_I", d.ack),
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Instance.Input("D_ERR_I", d.err),
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Instance.Input("D_RTY_I", 0))
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def get_fragment(self):
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comb = [
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self.ibus.adr.eq(self._i_adr_o[2:]),
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self.dbus.adr.eq(self._d_adr_o[2:])
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]
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return Fragment(comb=comb, specials={self._inst})
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cpus = [LM32() for i in range(4)]
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frag = Fragment()
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for cpu in cpus:
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frag += cpu.get_fragment()
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print(verilog.convert(frag, {cpus[0].interrupt}))
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