190 lines
6.0 KiB
Python
190 lines
6.0 KiB
Python
import os
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from misoclib import identifier
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from litescope.common import *
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from litescope.bridge.uart2wb import LiteScopeUART2WB
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from litescope.frontend.la import LiteScopeLA
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from litescope.core.port import LiteScopeTerm
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from liteeth.common import *
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from liteeth.generic import *
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from liteeth.phy.gmii import LiteEthPHYGMII
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.core.etherbone import LiteEthEtherbone
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.reset = Signal()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 166MHz
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p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
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]
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class GenSoC(Module):
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csr_base = 0x00000000
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csr_data_width = 32
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csr_map = {
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"bridge": 0,
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"identifier": 1,
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}
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interrupt_map = {}
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cpu_type = None
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def __init__(self, platform, clk_freq):
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self.clk_freq = clk_freq
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# UART <--> Wishbone bridge
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self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
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# CSR bridge 0x00000000 (shadow @0x00000000)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.bridge.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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# CSR
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self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def add_cpu_memory_region(self, name, origin, length):
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self.cpu_memory_regions.append((name, origin, length))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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class EtherboneSoC(GenSoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"phy": 11,
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"core": 12
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}
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csr_map.update(GenSoC.csr_map)
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def __init__(self, platform):
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clk_freq = 166*1000000
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GenSoC.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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# Ethernet PHY and UDP/IP
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self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.core = LiteEthUDPIPCore(self.phy, 0x10e2d5000000, convert_ip("192.168.1.40"), clk_freq)
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# Etherbone
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self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
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self.add_wb_master(self.etherbone.master.bus)
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self.submodules.sram = wishbone.SRAM(1024)
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self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
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class EtherboneSoCDevel(EtherboneSoC, AutoCSR):
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csr_map = {
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"la": 20
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}
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csr_map.update(EtherboneSoC.csr_map)
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def __init__(self, platform):
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EtherboneSoC.__init__(self, platform)
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debug = (
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# mmap stream from HOST
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self.etherbone.master.sink.stb,
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self.etherbone.master.sink.sop,
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self.etherbone.master.sink.eop,
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self.etherbone.master.sink.ack,
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self.etherbone.master.sink.we,
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self.etherbone.master.sink.count,
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self.etherbone.master.sink.base_addr,
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self.etherbone.master.sink.be,
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self.etherbone.master.sink.addr,
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self.etherbone.master.sink.data,
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# mmap stream to HOST
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self.etherbone.master.source.stb,
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self.etherbone.master.source.sop,
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self.etherbone.master.source.eop,
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self.etherbone.master.source.ack,
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self.etherbone.master.source.we,
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self.etherbone.master.source.count,
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self.etherbone.master.source.base_addr,
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self.etherbone.master.source.be,
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self.etherbone.master.source.addr,
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self.etherbone.master.source.data,
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# etherbone wishbone master
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self.etherbone.master.bus.dat_w,
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self.etherbone.master.bus.dat_r,
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self.etherbone.master.bus.adr,
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self.etherbone.master.bus.sel,
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self.etherbone.master.bus.cyc,
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self.etherbone.master.bus.stb,
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self.etherbone.master.bus.ack,
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self.etherbone.master.bus.we,
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self.etherbone.master.bus.cti,
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self.etherbone.master.bus.bte,
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self.etherbone.master.bus.err
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)
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self.submodules.la = LiteScopeLA(debug, 4096)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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def do_finalize(self):
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EtherboneSoC.do_finalize(self)
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def do_exit(self, vns):
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self.la.export(vns, "test/la.csv")
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default_subtarget = EtherboneSoC
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