151 lines
4.5 KiB
Python
151 lines
4.5 KiB
Python
from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthEtherboneRecordPacketizer(LiteEthPacketizer):
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def __init__(self):
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LiteEthPacketizer.__init__(self,
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eth_etherbone_record_description(32),
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eth_etherbone_packet_user_description(32),
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etherbone_record_header,
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etherbone_record_header_len)
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class LiteEthEtherboneRecordDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_etherbone_packet_user_description(32),
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eth_etherbone_record_description(32),
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etherbone_record_header,
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etherbone_record_header_len)
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class LiteEthEtherboneRecordReceiver(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_etherbone_record_description(32))
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self.wr_source = wr_source = Source(eth_etherbone_mmap_description(32))
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self.rd_source = rd_source = Source(eth_etherbone_mmap_description(32))
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###
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self.submodules.base_addr = base_addr = FlipFlop(32)
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self.comb += base_addr.d.eq(sink.data)
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self.submodules.counter = counter = Counter(max=512)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(1),
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counter.reset.eq(1),
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If(sink.stb & sink.sop,
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base_addr.ce.eq(1),
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If(sink.wcount,
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NextState("RECEIVE_READS")
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).Elif(sink.rcount,
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NextState("RECEIVE_READS")
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)
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)
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)
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fsm.act("RECEIVE_WRITES",
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wr_source.stb.eq(sink.stb),
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wr_source.sop.eq(counter.value == 0),
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wr_source.eop.eq(counter.value == sink.wcount-1),
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wr_source.count.eq(sink.wcount),
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wr_source.be.eq(sink.byte_enable),
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wr_source.addr.eq(base_addr.q + counter.value),
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wr_source.data.eq(sink.data),
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sink.ack.eq(wr_source.ack),
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If(wr_source.stb & wr_source.ack,
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counter.ce.eq(1),
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If(wr_source.eop,
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If(sink.rcount,
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NextState("RECEIVE_BASE_RET_ADDR")
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).Else(
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NextState("IDLE")
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)
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)
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)
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)
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fsm.act("RECEIVE_BASE_RET_ADDR",
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counter.reset.eq(1),
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If(sink.stb & sink.sop,
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base_addr.ce.eq(1),
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NextState("RECEIVE_READS")
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)
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)
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fsm.act("RECEIVE_READS",
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rd_source.stb.eq(sink.stb),
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rd_source.sop.eq(counter.value == 0),
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rd_source.eop.eq(counter.value == sink.rcount-1),
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rd_source.count.eq(sink.rcount),
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rd_source.base_addr.eq(base_addr.q),
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rd_source.addr.eq(sink.data),
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sink.ack.eq(rd_source.ack),
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If(rd_source.stb & rd_source.ack,
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counter.ce.eq(1),
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If(rd_source.eop,
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NextState("IDLE")
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)
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)
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)
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# Note: for now only support writes from the FPGA
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class LiteEthEtherboneRecordSender(Module):
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def __init__(self):
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self.wr_sink = wr_sink = Sink(eth_etherbone_mmap_description(32))
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self.rd_sink = rd_sink = Sink(eth_etherbone_mmap_description(32))
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self.source = source = Source(eth_etherbone_record_description(32))
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###
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self.submodules.wr_buffer = wr_buffer = PacketBuffer(eth_etherbone_mmap_description(32), 512)
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self.comb += Record.connect(wr_sink, wr_buffer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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wr_buffer.source.ack.eq(1),
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If(wr_buffer.source.stb & wr_buffer.source.sop,
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wr_buffer.source.ack.eq(0),
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NextState("SEND_BASE_ADDRESS")
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)
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)
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self.comb += [
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source.byte_enable.eq(wr_buffer.source.be),
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source.wcount.eq(wr_buffer.source.count),
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source.rcount.eq(0)
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]
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fsm.act("SEND_BASE_ADDRESS",
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source.stb.eq(wr_buffer.source.stb),
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source.sop.eq(1),
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source.eop.eq(0),
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source.data.eq(wr_buffer.source.base_addr),
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If(source.ack,
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NextState("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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source.stb.eq(wr_buffer.source.stb),
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source.sop.eq(0),
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source.eop.eq(wr_buffer.source.eop),
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source.data.eq(wr_buffer.source.data),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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# Note: for now only support 1 record per packet
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class LiteEthEtherboneRecord(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
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self.source = source = Sink(eth_etherbone_packet_user_description(32))
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###
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self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
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self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver()
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self.comb += [
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Record.connect(sink, depacketizer.sink),
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Record.connect(depacketizer.source, receiver.sink)
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]
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self.submodules.sender = sender = LiteEthEtherboneRecordSender()
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self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
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self.comb += [
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Record.connect(sender.source, packetizer.sink),
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Record.connect(packetizer.source, source)
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]
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