litex/migen
2012-02-15 18:23:31 +01:00
..
actorlib Use enumerate(x) instead of zip(range(x), x) 2012-02-02 21:28:00 +01:00
bank bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY 2012-02-15 18:23:31 +01:00
bus bus: add DFI 2012-02-15 18:09:14 +01:00
corelogic Use double quotes for all strings 2012-02-14 13:12:43 +01:00
fhdl fhdl: do not attempt slicing non-array signals to keep Verilog happy 2012-02-06 18:07:02 +01:00
flow Use double quotes for all strings 2012-02-14 13:12:43 +01:00
__init__.py