Robert Jordens f26ad97624 decorators: fix ControlInserter		2015-04-05 14:44:03 +08:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
bitcontainer.py	migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)	2013-12-10 23:32:12 +01:00
decorators.py	decorators: fix ControlInserter	2015-04-05 14:44:03 +08:00
edif.py	Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"	2015-03-30 19:41:16 +08:00
module.py	fhdl/visit: fix TransformModule	2015-03-14 17:45:11 +01:00
namer.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
simplify.py	fhdl/decorators: make the transform logic more idiomatic	2015-04-04 19:16:50 +08:00
specials.py	Revert "migen/fhdl: pass fdict filename --> contents to specials"	2015-03-30 19:41:13 +08:00
std.py	fhdl/std: add FinalizeError import	2015-01-23 00:23:41 +08:00
structure.py	Raise exception when not using correct boolean operators	2014-10-27 19:40:22 +08:00
tools.py	fhdl/tools: do not attempt to rename sync clock domain if it does not exist	2014-11-21 14:51:05 -08:00
tracer.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
verilog.py	Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"	2015-03-30 19:41:16 +08:00
visit.py	fhdl/visit: remove TransformModule	2015-04-04 20:12:22 +08:00