Benjamin Herrenschmidt f28f247130 soc: Don't create a wishbone slave to LiteDRAM with no CPU ... When creating a standalone LiteDRAM core with no CPU, there is no need to create a wishbone slave to LiteDRAM interface. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2020-05-12 21:30:19 +10:00
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cores	Merge branch 'master' into cpu-imac-config-for-vexriscv	2020-05-11 08:58:20 +02:00
doc	soc/doc/csr: allow CSRField.reset to be a Migen Constant.	2020-03-23 18:47:41 +01:00
integration	soc: Don't create a wishbone slave to LiteDRAM with no CPU	2020-05-12 21:30:19 +10:00
interconnect	Small fixups to address compiler warnings etc.	2020-05-07 09:26:46 +01:00
software	Merge branch 'master' into rdimm_bside_init	2020-05-11 09:42:35 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00