165 lines
4.8 KiB
Python
165 lines
4.8 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered as SyncFIFO
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import chooser, displacer
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from migen.flow.plumbing import Buffer
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from misoclib.com.litepcie.common import *
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def descriptor_layout(with_user_id=False):
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layout = [
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("address", 32),
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("length", 16)
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]
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if with_user_id:
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layout += [("user_id", 8)]
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return EndpointDescription(layout, packetized=True)
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class DMARequestTable(Module, AutoCSR):
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def __init__(self, depth):
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self.source = source = Source(descriptor_layout())
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aw = flen(source.address)
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lw = flen(source.length)
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self._value = CSRStorage(aw+lw)
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self._we = CSR()
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self._loop_prog_n = CSRStorage()
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self._loop_status = CSRStatus(32)
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self._level = CSRStatus(log2_int(depth))
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self._flush = CSR()
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self.irq = Signal()
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# # #
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# CSR signals
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value = self._value.storage
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we = self._we.r & self._we.re
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loop_prog_n = self._loop_prog_n.storage
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loop_index = self._loop_status.status[:log2_int(depth)]
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loop_count = self._loop_status.status[16:]
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level = self._level.status
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flush = self._flush.r & self._flush.re
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# FIFO
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# instance
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fifo_layout = [("address", aw), ("length", lw), ("start", 1)]
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fifo = InsertReset(SyncFIFO(fifo_layout, depth))
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self.submodules += fifo
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self.comb += [
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fifo.reset.eq(flush),
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level.eq(fifo.level)
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]
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# write part
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self.sync += [
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# in "loop" mode, each data output of the fifo is
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# written back
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If(loop_prog_n,
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fifo.din.address.eq(fifo.dout.address),
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fifo.din.length.eq(fifo.dout.length),
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fifo.din.start.eq(fifo.dout.start),
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fifo.we.eq(fifo.re)
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# in "program" mode, fifo input is connected
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# to registers
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).Else(
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fifo.din.address.eq(value[:aw]),
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fifo.din.length.eq(value[aw:aw+lw]),
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fifo.din.start.eq(~fifo.readable),
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fifo.we.eq(we)
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)
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]
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# read part
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self.comb += [
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source.stb.eq(fifo.readable),
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fifo.re.eq(source.stb & source.ack),
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source.address.eq(fifo.dout.address),
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source.length.eq(fifo.dout.length)
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]
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# loop_index, loop_count
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# used by the software for synchronization in
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# "loop" mode
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self.sync += \
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If(flush,
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loop_index.eq(0),
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loop_count.eq(0),
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).Elif(source.stb & source.ack,
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If(fifo.dout.start,
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loop_index.eq(0),
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loop_count.eq(loop_count+1)
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).Else(
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loop_index.eq(loop_index+1)
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)
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)
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# IRQ
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self.comb += self.irq.eq(source.stb & source.ack)
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class DMARequestSplitter(Module, AutoCSR):
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def __init__(self, max_size, buffered=True):
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self.sink = sink = Sink(descriptor_layout())
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if buffered:
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self.submodules.buffer = Buffer(descriptor_layout(True))
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source = self.buffer.d
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self.source = self.buffer.q
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else:
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self.source = source = Source(descriptor_layout(True))
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# # #
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offset = Signal(32)
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clr_offset = Signal()
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inc_offset = Signal()
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self.sync += \
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If(clr_offset,
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offset.eq(0)
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).Elif(inc_offset,
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offset.eq(offset + max_size)
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)
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user_id = Signal(8)
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self.sync += \
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If(sink.stb & sink.ack,
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user_id.eq(user_id+1)
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)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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length = Signal(16)
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update_length = Signal()
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self.sync += If(update_length, length.eq(sink.length))
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fsm.act("IDLE",
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sink.ack.eq(1),
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clr_offset.eq(1),
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If(sink.stb,
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update_length.eq(1),
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sink.ack.eq(0),
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NextState("RUN")
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)
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)
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fsm.act("RUN",
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source.stb.eq(1),
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source.address.eq(sink.address + offset),
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source.user_id.eq(user_id),
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If((length - offset) > max_size,
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source.length.eq(max_size),
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inc_offset.eq(source.ack)
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).Else(
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source.length.eq(length - offset),
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If(source.ack,
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NextState("ACK")
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)
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)
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)
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fsm.act("ACK",
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sink.ack.eq(1),
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NextState("IDLE")
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)
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