73 lines
2.7 KiB
Python
73 lines
2.7 KiB
Python
from liteeth.common import *
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from liteeth.mac.core import gap, preamble, crc, last_be
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class LiteEthMACCore(Module, AutoCSR):
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def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
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if dw < phy.dw:
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw))
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rx_pipeline = [phy]
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tx_pipeline = [phy]
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# Interpacket gap
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tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
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rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
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self.submodules += tx_gap_inserter, rx_gap_checker
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tx_pipeline += [tx_gap_inserter]
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rx_pipeline += [rx_gap_checker]
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# Preamble / CRC
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if with_hw_preamble_crc:
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self._hw_preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
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preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
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self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
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self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
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# CRC insert/check
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crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
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crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
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self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
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self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
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tx_pipeline += [preamble_inserter, crc32_inserter]
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rx_pipeline += [preamble_checker, crc32_checker]
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# Delimiters
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if dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
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rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
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self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
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self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
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tx_pipeline += [tx_last_be]
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rx_pipeline += [rx_last_be]
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# Converters
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if dw != phy.dw:
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reverse = endianness == "big"
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tx_converter = Converter(eth_phy_description(dw), eth_phy_description(phy.dw), reverse=reverse)
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rx_converter = Converter(eth_phy_description(phy.dw), eth_phy_description(dw), reverse=reverse)
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self.submodules += RenameClockDomains(tx_converter, "eth_tx")
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self.submodules += RenameClockDomains(rx_converter, "eth_rx")
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tx_pipeline += [tx_converter]
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rx_pipeline += [rx_converter]
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# Cross Domain Crossing
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tx_cdc = AsyncFIFO(eth_phy_description(dw), 8)
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rx_cdc = AsyncFIFO(eth_phy_description(dw), 8)
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self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
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self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
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tx_pipeline += [tx_cdc]
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rx_pipeline += [rx_cdc]
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# Graph
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self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
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self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
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self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
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