60 lines
1.3 KiB
Verilog
60 lines
1.3 KiB
Verilog
module s6ddrphy #(
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parameter NUM_AD = 0,
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parameter NUM_BA = 0,
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parameter NUM_D = 0 /* < number of data lines per DFI phase */
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) (
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/* Clocks */
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input sys_clk,
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input clk2x_90,
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input clk4x_wr,
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input clk4x_wr_strb,
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input clk4x_rd,
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input clk4x_rd_strb,
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/* DFI phase 0 */
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input [NUM_AD-1:0] dfi_address_p0,
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input [NUM_BA-1:0] dfi_bank_p0,
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input dfi_cs_n_p0,
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input dfi_cke_p0,
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input dfi_ras_n_p0,
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input dfi_cas_n_p0,
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input dfi_we_n_p0,
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input dfi_wrdata_en_p0,
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input [NUM_D/8-1:0] dfi_wrdata_mask_p0,
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input [NUM_D-1:0] dfi_wrdata_p0,
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input dfi_rddata_en_p0,
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output [NUM_D-1:0] dfi_rddata_w0,
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output dfi_rddata_valid_w0,
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/* DFI phase 1 */
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input [NUM_AD-1:0] dfi_address_p1,
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input [NUM_BA-1:0] dfi_bank_p1,
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input dfi_cs_n_p1,
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input dfi_cke_p1,
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input dfi_ras_n_p1,
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input dfi_cas_n_p1,
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input dfi_we_n_p1,
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input dfi_wrdata_en_p1,
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input [NUM_D/8-1:0] dfi_wrdata_mask_p1,
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input [NUM_D-1:0] dfi_wrdata_p1,
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input dfi_rddata_en_p1,
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output [NUM_D-1:0] dfi_rddata_w1,
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output dfi_rddata_valid_w1,
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/* DDR SDRAM pads */
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output sd_clk_out_p,
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output sd_clk_out_n,
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output [NUM_AD-1:0] sd_a,
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output [NUM_BA-1:0] sd_ba,
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output sd_cs_n,
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output sd_cke,
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output sd_ras_n,
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output sd_cas_n,
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output sd_we_n,
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inout [NUM_D/2-1:0] sd_dq,
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output [NUM_D/16-1:0] sd_dm,
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inout [NUM_D/16-1:0] sd_dqs
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);
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endmodule
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