23 lines
612 B
Python
23 lines
612 B
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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from migen.bank import description, csrgen
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ninputs = 4
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noutputs = 4
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oreg = description.RegisterField("o", noutputs)
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ireg = description.RegisterRaw("i", ninputs)
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# input path
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gpio_in = Signal(BV(ninputs))
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gpio_in_s = Signal(BV(ninputs)) # synchronizer
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insync = [gpio_in_s.eq(gpio_in), ireg.w.eq(gpio_in_s)]
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inf = Fragment(sync=insync)
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bank = csrgen.Bank([oreg, ireg])
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f = bank.get_fragment() + inf
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oreg.field.r.name_override = "gpio_out"
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i = bank.interface
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v = verilog.convert(f, {i.d_o, oreg.field.r, i.a_i, i.we_i, i.d_i, gpio_in})
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print(v)
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