Florent Kermarrec fd7ed6c1ec utils/litex_sim: fix main_ram_size		2019-03-16 21:25:02 +01:00
..
__init__.py	[fix] utils was not installed from pip	2019-03-07 09:40:58 +01:00
litex_read_verilog.py	utils/litex_read_verilog: fix generated indent on instance	2018-11-22 17:33:46 +01:00
litex_server.py	utils/litex_server: allow specify uart_baudrate as float	2019-01-03 10:38:14 +01:00
litex_sim.py	utils/litex_sim: fix main_ram_size	2019-03-16 21:25:02 +01:00
litex_term.py	create utils directory and move the litex utils to it	2018-11-16 14:37:19 +01:00