Florent Kermarrec f512971d9e gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)		2016-03-25 13:22:26 +01:00
..
boards	boards/targets: change mode (add +x)	2016-01-01 18:37:20 +01:00
build	gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator	2016-03-21 19:15:40 +01:00
gen	gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)	2016-03-25 13:22:26 +01:00
soc	soc/interconnect/stream_sim: use passive generators and some cleanup	2016-03-23 01:04:33 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00