66 lines
1.5 KiB
Python
66 lines
1.5 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.record import *
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from migen.genlib.fsm import *
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from migen.flow.actor import *
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# Generates integers from start to maximum-1
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class IntSequence(Module):
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def __init__(self, nbits, offsetbits=0, step=1):
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parameters_layout = [("maximum", nbits)]
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if offsetbits:
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parameters_layout.append(("offset", offsetbits))
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self.parameters = Sink(parameters_layout)
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self.source = Source([("value", max(nbits, offsetbits))])
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self.busy = Signal()
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###
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load = Signal()
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ce = Signal()
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last = Signal()
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maximum = Signal(nbits)
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if offsetbits:
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offset = Signal(offsetbits)
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counter = Signal(nbits)
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if step > 1:
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self.comb += last.eq(counter + step >= maximum)
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else:
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self.comb += last.eq(counter + 1 == maximum)
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self.sync += [
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If(load,
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counter.eq(0),
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maximum.eq(self.parameters.payload.maximum),
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offset.eq(self.parameters.payload.offset) if offsetbits else None
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).Elif(ce,
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If(last,
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counter.eq(0)
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).Else(
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counter.eq(counter + step)
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)
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)
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]
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if offsetbits:
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self.comb += self.source.payload.value.eq(counter + offset)
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else:
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self.comb += self.source.payload.value.eq(counter)
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fsm = FSM("IDLE", "ACTIVE")
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self.submodules += fsm
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fsm.act(fsm.IDLE,
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load.eq(1),
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self.parameters.ack.eq(1),
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If(self.parameters.stb, fsm.next_state(fsm.ACTIVE))
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)
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fsm.act(fsm.ACTIVE,
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self.busy.eq(1),
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self.source.stb.eq(1),
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If(self.source.ack,
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ce.eq(1),
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If(last, fsm.next_state(fsm.IDLE))
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)
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)
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