227 lines
6.1 KiB
Python
227 lines
6.1 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.flow.actor import *
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def _rawbits_layout(l):
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if isinstance(l, int):
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return [("rawbits", l)]
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else:
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return l
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class Cast(CombinatorialActor):
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def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False, packetized=False):
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self.sink = Sink(_rawbits_layout(layout_from), packetized)
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self.source = Source(_rawbits_layout(layout_to), packetized)
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CombinatorialActor.__init__(self)
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###
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sigs_from = self.sink.payload.flatten()
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if reverse_from:
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sigs_from = list(reversed(sigs_from))
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sigs_to = self.source.payload.flatten()
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if reverse_to:
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sigs_to = list(reversed(sigs_to))
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if sum(flen(s) for s in sigs_from) != sum(flen(s) for s in sigs_to):
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raise TypeError
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self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
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def pack_layout(l, n):
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return [("chunk"+str(i), l) for i in range(n)]
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class Unpack(Module):
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def __init__(self, n, layout_to, reverse=False, packetized=False):
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self.sink = Sink(pack_layout(layout_to, n), packetized)
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self.source = Source(layout_to, packetized)
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self.busy = Signal()
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###
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mux = Signal(max=n)
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first = Signal()
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last = Signal()
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self.comb += [
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first.eq(mux == 0),
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last.eq(mux == (n-1)),
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self.source.stb.eq(self.sink.stb),
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self.sink.ack.eq(last & self.source.ack)
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]
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self.sync += [
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If(self.source.stb & self.source.ack,
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If(last,
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mux.eq(0)
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).Else(
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mux.eq(mux + 1)
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)
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)
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]
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cases = {}
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for i in range(n):
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chunk = n-i-1 if reverse else i
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cases[i] = [self.source.payload.raw_bits().eq(getattr(self.sink.payload, "chunk"+str(chunk)).raw_bits())]
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self.comb += Case(mux, cases).makedefault()
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if packetized:
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self.comb += [
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self.source.sop.eq(self.source.stb & self.sink.sop & first),
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self.source.eop.eq(self.source.stb & self.sink.eop & last)
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]
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class Pack(Module):
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def __init__(self, layout_from, n, reverse=False, packetized=False):
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self.sink = sink = Sink(layout_from, packetized)
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self.source = source = Source(pack_layout(layout_from, n), packetized)
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self.busy = Signal()
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###
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demux = Signal(max=n)
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load_part = Signal()
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strobe_all = Signal()
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cases = {}
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for i in range(n):
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chunk = n-i-1 if reverse else i
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cases[i] = [getattr(source.payload, "chunk"+str(chunk)).raw_bits().eq(sink.payload.raw_bits())]
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self.comb += [
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self.busy.eq(strobe_all),
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sink.ack.eq(~strobe_all | source.ack),
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source.stb.eq(strobe_all),
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load_part.eq(sink.stb & sink.ack)
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]
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if packetized:
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demux_last = ((demux == (n - 1)) | sink.eop)
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else:
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demux_last = (demux == (n - 1))
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self.sync += [
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If(source.ack, strobe_all.eq(0)),
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If(load_part,
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Case(demux, cases),
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If(demux_last,
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demux.eq(0),
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strobe_all.eq(1)
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).Else(
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demux.eq(demux + 1)
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)
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)
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]
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if packetized:
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sop = Signal()
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eop = Signal()
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self.sync += [
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If(source.stb & source.ack,
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sop.eq(load_part & sink.sop)
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).Else(
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sop.eq((load_part & sink.sop) | sop)
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),
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eop.eq(load_part & sink.eop)
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]
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self.comb += [
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source.sop.eq(source.stb & sop),
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source.eop.eq(source.stb & eop),
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]
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class Chunkerize(CombinatorialActor):
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def __init__(self, layout_from, layout_to, n, reverse=False, packetized=False):
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self.sink = Sink(layout_from, packetized)
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self.source = Source(pack_layout(layout_to, n), packetized)
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CombinatorialActor.__init__(self)
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###
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for i in range(n):
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chunk = n-i-1 if reverse else i
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for f in layout_from:
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src = getattr(self.sink, f[0])
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dst = getattr(getattr(self.source, "chunk"+str(chunk)), f[0])
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self.comb += dst.eq(src[i*flen(src)//n:(i+1)*flen(src)//n])
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class Unchunkerize(CombinatorialActor):
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def __init__(self, layout_from, n, layout_to, reverse=False, packetized=False):
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self.sink = Sink(pack_layout(layout_from, n), packetized)
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self.source = Source(layout_to, packetized)
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CombinatorialActor.__init__(self)
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###
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for i in range(n):
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chunk = n-i-1 if reverse else i
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for f in layout_from:
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src = getattr(getattr(self.sink, "chunk"+str(chunk)), f[0])
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dst = getattr(self.source, f[0])
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self.comb += dst[i*flen(dst)//n:(i+1)*flen(dst)//n].eq(src)
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class Converter(Module):
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def __init__(self, layout_from, layout_to, packetized=False, reverse=False):
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self.sink = Sink(layout_from, packetized)
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self.source = Source(layout_to, packetized)
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self.busy = Signal()
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###
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width_from = flen(self.sink.payload.raw_bits())
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width_to = flen(self.source.payload.raw_bits())
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# downconverter
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if width_from > width_to:
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if width_from % width_to:
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raise ValueError
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ratio = width_from//width_to
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self.submodules.chunkerize = Chunkerize(layout_from, layout_to, ratio, reverse, packetized)
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self.submodules.unpack = Unpack(ratio, layout_to, packetized=packetized)
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self.comb += [
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Record.connect(self.sink, self.chunkerize.sink),
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Record.connect(self.chunkerize.source, self.unpack.sink),
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Record.connect(self.unpack.source, self.source),
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self.busy.eq(self.unpack.busy)
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]
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# upconverter
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elif width_to > width_from:
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if width_to % width_from:
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raise ValueError
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ratio = width_to//width_from
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self.submodules.pack = Pack(layout_from, ratio, packetized=packetized)
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self.submodules.unchunkerize = Unchunkerize(layout_from, ratio, layout_to, reverse, packetized)
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self.comb += [
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Record.connect(self.sink, self.pack.sink),
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Record.connect(self.pack.source, self.unchunkerize.sink),
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Record.connect(self.unchunkerize.source, self.source),
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self.busy.eq(self.pack.busy)
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]
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# direct connection
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else:
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self.comb += Record.connect(self.sink, self.source)
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class Pipeline(Module):
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def __init__(self, *modules):
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self.busy = Signal()
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n = len(modules)
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m = modules[0]
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# expose sink of first module
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# if available
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if hasattr(m, "sink"):
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self.sink = m.sink
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if hasattr(m, "busy"):
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busy = m.busy
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else:
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busy = 0
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for i in range(1, n):
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m_n = modules[i]
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if hasattr(m_n, "busy"):
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busy_n = m_n.busy
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else:
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busy_n = 0
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self.comb += m.source.connect(m_n.sink)
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m = m_n
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busy = busy | busy_n
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# expose source of last module
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# if available
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if hasattr(m, "source"):
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self.source = m.source
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self.comb += self.busy.eq(busy)
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