litex/litex/soc
2015-11-12 00:54:40 +01:00
..
cores soc/interconnect: add wishbonebridge and uart bridge 2015-11-12 00:52:36 +01:00
integration soc/integration/soc_core: add support for SoCs without CPU 2015-11-12 00:50:23 +01:00
interconnect soc/interconnect: add packet 2015-11-12 00:54:40 +01:00
software add LICENSE, update copyrights, add Migen install instructions 2015-11-11 13:22:39 +01:00
tools soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b 2015-11-10 16:51:51 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
MISOC_LICENSE litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00