58 lines
1.5 KiB
Python
58 lines
1.5 KiB
Python
from migen.fhdl.structure import *
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from migen.bus.simple import *
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def phase_description(a, ba, d):
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return Description(
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(M_TO_S, "address", a),
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(M_TO_S, "bank", ba),
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(M_TO_S, "cas_n", 1),
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(M_TO_S, "cke", 1),
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(M_TO_S, "cs_n", 1),
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(M_TO_S, "ras_n", 1),
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(M_TO_S, "we_n", 1),
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(M_TO_S, "wrdata", d),
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(M_TO_S, "wrdata_en", 1),
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(M_TO_S, "wrdata_mask", d//8),
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(M_TO_S, "rddata_en", 1),
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(S_TO_M, "rddata", d),
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(S_TO_M, "rddata_valid", 1)
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)
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class Interface:
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def __init__(self, a, ba, d, nphases=1):
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self.pdesc = phase_description(a, ba, d)
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self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
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# Returns pairs (DFI-mandated signal name, Migen signal object)
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def get_standard_names(self, m2s=True, s2m=True):
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r = []
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add_suffix = len(self.phases) > 1
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for n, phase in enumerate(self.phases):
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for signal in self.pdesc.desc:
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if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M):
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if add_suffix:
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if signal[0] == M_TO_S:
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suffix = "_p" + str(n)
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else:
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suffix = "_w" + str(n)
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else:
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suffix = ""
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r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))
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return r
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def interconnect_stmts(master, slave):
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r = []
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for pm, ps in zip(master.phases, slave.phases):
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r += simple_interconnect_stmts(master.pdesc, pm, [ps])
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return r
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class Interconnect:
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def __init__(self, master, slave):
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self.master = master
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self.slave = slave
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def get_fragment(self):
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return Fragment(interconnect_stmts(self.master, self.slave))
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