134 lines
2.6 KiB
Python
134 lines
2.6 KiB
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.bus import csr
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from migen.sim.generic import run_simulation
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from migen.bus.transactions import *
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from miscope.std import *
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from miscope.storage import *
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from mibuild.tools import write_to_file
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from miscope.tools.regs import *
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from miscope.tools.truthtable import *
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from cpuif import *
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class Csr2Trans():
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def __init__(self):
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self.t = []
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def write_csr(self, adr, value):
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self.t.append(TWrite(adr//4, value))
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def read_csr(self, adr):
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self.t.append(TRead(adr//4))
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return 0
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triggered = False
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dat = 0
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rec_done = False
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dat_rdy = False
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rec_length = 128
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def csr_configure(bus, regs):
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# Length
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regs.recorder_length.write(rec_length)
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# Offset
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regs.recorder_offset.write(0)
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# Trigger
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regs.recorder_trigger.write(1)
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return bus.t
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def csr_read_data(bus, regs):
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for i in range(rec_length+100):
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regs.recorder_read_dat.read()
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regs.recorder_read_en.write(1)
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return bus.t
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def csr_transactions(bus, regs):
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for t in csr_configure(bus, regs):
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yield t
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for t in range(100):
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yield None
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global triggered
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triggered = True
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for t in range(512):
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yield None
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for t in csr_read_data(bus, regs):
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yield t
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for t in range(100):
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yield None
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class TB(Module):
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csr_base = 0
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csr_map = {
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"recorder": 1,
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}
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def __init__(self, addrmap=None):
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self.csr_base = 0
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# Recorder
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self.submodules.recorder = Recorder(32, 1024)
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# Csr
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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# Csr Master
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csr_header = get_csr_csv(self.csr_base, self.csrbankarray)
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write_to_file("csr.csv", csr_header)
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bus = Csr2Trans()
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regs = build_map(addrmap, bus.read_csr, bus.write_csr)
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self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
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self.submodules.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
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# Recorder Data
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def recorder_data(self, selfp):
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selfp.recorder.dat_sink.stb = 1
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if not hasattr(self, "cnt"):
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self.cnt = 0
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self.cnt += 1
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selfp.recorder.dat_sink.dat = self.cnt
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global triggered
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if triggered:
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selfp.recorder.trig_sink.stb = 1
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selfp.recorder.trig_sink.hit = 1
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triggered = False
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else:
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selfp.recorder.trig_sink.stb = 0
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selfp.recorder.trig_sink.hit = 0
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# Simulation
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def end_simulation(self, selfp):
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if self.master.done:
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raise StopSimulation
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def do_simulation(self, selfp):
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self.recorder_data(selfp)
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self.end_simulation(selfp)
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def main():
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tb = TB(addrmap="csr.csv")
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run_simulation(tb, ncycles=2000, vcd_name="tb_recorder_csr.vcd")
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print("Sim Done")
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input()
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main() |