103 lines
2.5 KiB
Python
103 lines
2.5 KiB
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.bus import csr
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from migen.sim.generic import run_simulation
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from migen.bus.transactions import *
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from miscope.std import *
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from miscope.trigger import *
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from mibuild.tools import write_to_file
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from miscope.tools.regs import *
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from miscope.tools.truthtable import *
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from cpuif import *
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class Csr2Trans():
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def __init__(self):
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self.t = []
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def write_csr(self, adr, value):
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self.t.append(TWrite(adr//4, value))
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def read_csr(self, adr):
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self.t.append(TRead(adr//4))
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def csr_prog_mila(bus, regs):
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regs.trigger_port0_mask.write(0xFFFFFFFF)
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regs.trigger_port0_trig.write(0xDEADBEEF)
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regs.trigger_port1_mask.write(0xFFFFFFFF)
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regs.trigger_port1_trig.write(0xCAFEFADE)
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regs.trigger_port2_mask.write(0xFFFFFFFF)
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regs.trigger_port2_trig.write(0xDEADBEEF)
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regs.trigger_port3_mask.write(0xFFFFFFFF)
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regs.trigger_port3_trig.write(0xCAFEFADE)
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sum_tt = gen_truth_table("i1 & i2 & i3 & i4")
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sum_trans = []
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for i in range(len(sum_tt)):
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regs.trigger_sum_prog_adr.write(i)
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regs.trigger_sum_prog_dat.write(sum_tt[i])
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regs.trigger_sum_prog_we.write(1)
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return bus.t
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csr_done = False
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def csr_transactions(bus, regs):
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for t in csr_prog_mila(bus, regs):
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yield t
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global csr_done
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csr_done = True
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for t in range(100):
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yield None
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class TB(Module):
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csr_base = 0
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csr_map = {
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"trigger": 1,
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}
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def __init__(self, addrmap=None):
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self.csr_base = 0
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# Trigger
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term0 = Term(32)
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term1 = Term(32)
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term2 = Term(32)
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term3 = Term(32)
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self.submodules.trigger = Trigger(32, [term0, term1, term2, term3])
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# Csr
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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# Csr Master
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csr_header = get_csr_csv(self.csr_base, self.csrbankarray)
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write_to_file("csr.csv", csr_header)
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bus = Csr2Trans()
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regs = build_map(addrmap, bus.read_csr, bus.write_csr)
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self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
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self.submodules.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
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self.terms = [term0, term1, term2, term3]
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def do_simulation(self, selfp):
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for term in selfp.terms:
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term.sink.stb = 1
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if csr_done:
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selfp.terms[0].sink.dat = 0xDEADBEEF
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selfp.terms[1].sink.dat = 0xCAFEFADE
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selfp.terms[2].sink.dat = 0xDEADBEEF
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selfp.terms[3].sink.dat = 0xCAFEFADE
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def main():
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tb = TB(addrmap="csr.csv")
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run_simulation(tb, ncycles=2000, vcd_name="tb_trigger_csr.vcd")
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print("Sim Done")
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input()
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main()
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