184 lines
6.1 KiB
Python
184 lines
6.1 KiB
Python
import os, struct, subprocess, sys
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from decimal import Decimal
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from migen.fhdl.std import *
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from migen.fhdl.specials import SynthesisDirective
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from migen.genlib.cdc import *
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from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild import tools
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def _add_period_constraint(platform, clk, period):
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if period is not None:
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platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk";
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TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
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class CRG_SE(SimpleCRG):
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def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
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SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
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_add_period_constraint(platform, self._clk, period)
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class CRG_DS(Module):
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def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
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reset_less = rst_name is None
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self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
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self._clk = platform.request(clk_name)
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_add_period_constraint(platform, self._clk.p, period)
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self.specials += Instance("IBUFGDS",
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Instance.Input("I", self._clk.p),
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Instance.Input("IB", self._clk.n),
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Instance.Output("O", self.cd_sys.clk)
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)
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if not reset_less:
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if rst_invert:
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self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
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else:
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self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
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def _format_constraint(c):
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if isinstance(c, Pins):
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return "LOC=" + c.identifiers[0]
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elif isinstance(c, IOStandard):
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return "IOSTANDARD=" + c.name
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elif isinstance(c, Drive):
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return "DRIVE=" + str(c.strength)
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elif isinstance(c, Misc):
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return c.misc
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def _format_ucf(signame, pin, others, resname):
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fmt_c = []
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for c in [Pins(pin)] + others:
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fc = _format_constraint(c)
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if fc is not None:
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fmt_c.append(fc)
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fmt_r = resname[0] + ":" + str(resname[1])
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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return "NET \"" + signame + "\" " + " | ".join(fmt_c) + "; # " + fmt_r + "\n"
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def _build_ucf(named_sc, named_pc):
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r = ""
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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r += _format_ucf(sig + "(" + str(i) + ")", p, others, resname)
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else:
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r += _format_ucf(sig, pins[0], others, resname)
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if named_pc:
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r += "\n" + "\n\n".join(named_pc)
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return r
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def _build_files(device, sources, named_sc, named_pc, build_name):
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tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
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prj_contents = ""
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for filename, language in sources:
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prj_contents += language + " work " + filename + "\n"
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tools.write_to_file(build_name + ".prj", prj_contents)
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xst_contents = """run
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-ifn %s.prj
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-top top
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-ifmt MIXED
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-opt_mode SPEED
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-reduce_control_sets auto
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-register_balancing yes
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-ofn %s.ngc
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-p %s""" % (build_name, build_name, device)
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tools.write_to_file(build_name + ".xst", xst_contents)
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def _is_valid_version(path, v):
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try:
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Decimal(v)
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return os.path.isdir(os.path.join(path, v))
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except:
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return False
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def _run_ise(build_name, ise_path, source):
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if sys.platform == "win32" or sys.platform == "cygwin":
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source = False
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build_script_contents = "# Autogenerated by mibuild\nset -e\n"
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if source:
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vers = [ver for ver in os.listdir(ise_path) if _is_valid_version(ise_path, ver)]
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tools_version = max(vers)
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bits = struct.calcsize("P")*8
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xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits)
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build_script_contents += "source " + xilinx_settings_file + "\n"
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build_script_contents += """
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xst -ifn {build_name}.xst
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ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd
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map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
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par -ol high -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
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bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}.ncd {build_name}.bit
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""".format(build_name=build_name)
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build_script_file = "build_" + build_name + ".sh"
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tools.write_to_file(build_script_file, build_script_contents)
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r = subprocess.call(["bash", build_script_file])
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if r != 0:
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raise OSError("Subprocess failed")
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class XilinxNoRetimingImpl(Module):
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def __init__(self, reg):
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self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
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class XilinxNoRetiming:
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@staticmethod
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def lower(dr):
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return XilinxNoRetimingImpl(dr.reg)
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class XilinxMultiRegImpl(MultiRegImpl):
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def __init__(self, *args, **kwargs):
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MultiRegImpl.__init__(self, *args, **kwargs)
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self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
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for r in self.regs]
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class XilinxMultiReg:
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@staticmethod
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def lower(dr):
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return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
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class XilinxISEPlatform(GenericPlatform):
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = {
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NoRetiming: XilinxNoRetiming,
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MultiReg: XilinxMultiReg
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}
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
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def build(self, fragment, build_dir="build", build_name="top",
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ise_path="/opt/Xilinx", source=True, run=True):
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tools.mkdir_noerror(build_dir)
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os.chdir(build_dir)
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v_src, named_sc, named_pc = self.get_verilog(fragment)
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v_file = build_name + ".v"
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tools.write_to_file(v_file, v_src)
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sources = self.sources + [(v_file, "verilog")]
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_build_files(self.device, sources, named_sc, named_pc, build_name)
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if run:
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_run_ise(build_name, ise_path, source)
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os.chdir("..")
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def build_arg_ns(self, ns, *args, **kwargs):
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for n in ["build_dir", "build_name", "ise_path"]:
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attr = getattr(ns, n)
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if attr is not None:
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kwargs[n] = attr
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if ns.no_source:
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kwargs["source"] = False
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if ns.no_run:
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kwargs["run"] = False
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self.build(*args, **kwargs)
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def add_arguments(self, parser):
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parser.add_argument("--build-dir", default=None, help="Set the directory in which to generate files and run ISE")
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parser.add_argument("--build-name", default=None, help="Base name for the generated files")
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parser.add_argument("--ise-path", default=None, help="ISE installation path (without version directory)")
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parser.add_argument("--no-source", action="store_true", help="Do not source ISE settings file")
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parser.add_argument("--no-run", action="store_true", help="Only generate files, do not run ISE")
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