145 lines
3.8 KiB
Python
145 lines
3.8 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.bank.description import CSRStorage
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from migen.genlib.record import Record
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from migen.genlib.fsm import FSM, NextState
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from migen.actorlib import spi
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_hbits = 12
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_vbits = 12
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bpp = 32
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bpc = 10
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pixel_layout_s = [
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("pad", bpp-3*bpc),
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("r", bpc),
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("g", bpc),
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("b", bpc)
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]
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def pixel_layout(pack_factor):
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return [("p"+str(i), pixel_layout_s) for i in range(pack_factor)]
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bpc_phy = 8
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phy_layout_s = [
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("r", bpc_phy),
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("g", bpc_phy),
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("b", bpc_phy)
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]
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def phy_layout(pack_factor):
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r = [("hsync", 1), ("vsync", 1), ("de", 1)]
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for i in range(pack_factor):
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r.append(("p"+str(i), phy_layout_s))
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return r
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class FrameInitiator(spi.SingleGenerator):
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def __init__(self, bus_aw, pack_factor, ndmas=1):
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h_alignment_bits = log2_int(pack_factor)
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hbits_dyn = _hbits - h_alignment_bits
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bus_alignment_bits = h_alignment_bits + log2_int(bpp//8)
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layout = [
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("hres", hbits_dyn, 640, h_alignment_bits),
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("hsync_start", hbits_dyn, 656, h_alignment_bits),
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("hsync_end", hbits_dyn, 752, h_alignment_bits),
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("hscan", hbits_dyn, 800, h_alignment_bits),
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("vres", _vbits, 480),
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("vsync_start", _vbits, 492),
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("vsync_end", _vbits, 494),
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("vscan", _vbits, 525),
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("length", bus_aw + bus_alignment_bits, 640*480*bpp//8, bus_alignment_bits)
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]
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layout += [("base"+str(i), bus_aw + bus_alignment_bits, 0, bus_alignment_bits)
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for i in range(ndmas)]
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spi.SingleGenerator.__init__(self, layout, spi.MODE_CONTINUOUS)
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timing_subr = ["hres", "hsync_start", "hsync_end", "hscan",
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"vres", "vsync_start", "vsync_end", "vscan"]
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def dma_subr(self, i=0):
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return ["length", "base"+str(i)]
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class VTG(Module):
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def __init__(self, pack_factor):
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hbits_dyn = _hbits - log2_int(pack_factor)
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timing_layout = [
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("hres", hbits_dyn),
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("hsync_start", hbits_dyn),
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("hsync_end", hbits_dyn),
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("hscan", hbits_dyn),
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("vres", _vbits),
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("vsync_start", _vbits),
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("vsync_end", _vbits),
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("vscan", _vbits)]
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self.timing = Sink(timing_layout)
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self.pixels = Sink(pixel_layout(pack_factor))
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self.phy = Source(phy_layout(pack_factor))
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self.busy = Signal()
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###
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hactive = Signal()
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vactive = Signal()
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active = Signal()
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hcounter = Signal(hbits_dyn)
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vcounter = Signal(_vbits)
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skip = bpc - bpc_phy
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self.comb += [
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active.eq(hactive & vactive),
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If(active,
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[getattr(getattr(self.phy.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
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for p in ["p"+str(i) for i in range(pack_factor)] for c in ["r", "g", "b"]],
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self.phy.payload.de.eq(1)
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),
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self.pixels.ack.eq(self.phy.ack & active)
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]
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load_timing = Signal()
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tr = Record(timing_layout)
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self.sync += If(load_timing, tr.eq(self.timing.payload))
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generate_en = Signal()
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generate_frame_done = Signal()
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self.sync += [
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generate_frame_done.eq(0),
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If(generate_en,
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hcounter.eq(hcounter + 1),
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If(hcounter == 0, hactive.eq(1)),
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If(hcounter == tr.hres, hactive.eq(0)),
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If(hcounter == tr.hsync_start, self.phy.payload.hsync.eq(1)),
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If(hcounter == tr.hsync_end, self.phy.payload.hsync.eq(0)),
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If(hcounter == tr.hscan,
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hcounter.eq(0),
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If(vcounter == tr.vscan,
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vcounter.eq(0),
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generate_frame_done.eq(1)
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).Else(
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vcounter.eq(vcounter + 1)
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)
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),
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If(vcounter == 0, vactive.eq(1)),
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If(vcounter == tr.vres, vactive.eq(0)),
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If(vcounter == tr.vsync_start, self.phy.payload.vsync.eq(1)),
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If(vcounter == tr.vsync_end, self.phy.payload.vsync.eq(0))
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)
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]
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self.submodules.fsm = FSM()
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self.fsm.act("GET_TIMING",
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self.timing.ack.eq(1),
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load_timing.eq(1),
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If(self.timing.stb, NextState("GENERATE"))
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)
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self.fsm.act("GENERATE",
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self.busy.eq(1),
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If(~active | self.pixels.stb,
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self.phy.stb.eq(1),
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If(self.phy.ack, generate_en.eq(1))
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),
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If(generate_frame_done, NextState("GET_TIMING"))
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)
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