50 lines
1.2 KiB
Python
50 lines
1.2 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class ResolutionDetection(Module, AutoCSR):
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def __init__(self, nbits=11):
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self.vsync = Signal()
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self.de = Signal()
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self._hres = CSRStatus(nbits)
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self._vres = CSRStatus(nbits)
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###
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# Detect DE transitions
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de_r = Signal()
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pn_de = Signal()
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self.sync.pix += de_r.eq(self.de)
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self.comb += pn_de.eq(~self.de & de_r)
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# HRES
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hcounter = Signal(nbits)
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self.sync.pix += If(self.de,
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hcounter.eq(hcounter + 1)
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).Else(
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hcounter.eq(0)
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)
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hcounter_st = Signal(nbits)
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self.sync.pix += If(pn_de, hcounter_st.eq(hcounter))
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self.specials += MultiReg(hcounter_st, self._hres.status)
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# VRES
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vsync_r = Signal()
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p_vsync = Signal()
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self.sync.pix += vsync_r.eq(self.vsync),
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self.comb += p_vsync.eq(self.vsync & ~vsync_r)
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vcounter = Signal(nbits)
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self.sync.pix += If(p_vsync,
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vcounter.eq(0)
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).Elif(pn_de,
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vcounter.eq(vcounter + 1)
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)
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vcounter_st = Signal(nbits)
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self.sync.pix += If(p_vsync, vcounter_st.eq(vcounter))
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self.specials += MultiReg(vcounter_st, self._vres.status)
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