77 lines
1.4 KiB
Verilog
77 lines
1.4 KiB
Verilog
module minimac3_sync(
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input sys_clk,
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input phy_rx_clk,
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input phy_tx_clk,
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input [1:0] sys_rx_ready,
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output [1:0] sys_rx_done,
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output reg [10:0] sys_rx_count_0,
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output reg [10:0] sys_rx_count_1,
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input sys_tx_start,
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output sys_tx_done,
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input [10:0] sys_tx_count,
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output [1:0] phy_rx_ready,
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input [1:0] phy_rx_done,
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input [10:0] phy_rx_count_0,
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input [10:0] phy_rx_count_1,
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output phy_tx_start,
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input phy_tx_done,
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output reg [10:0] phy_tx_count
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);
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psync rx_ready_0(
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.clk1(sys_clk),
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.i(sys_rx_ready[0]),
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.clk2(phy_rx_clk),
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.o(phy_rx_ready[0])
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);
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psync rx_ready_1(
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.clk1(sys_clk),
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.i(sys_rx_ready[1]),
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.clk2(phy_rx_clk),
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.o(phy_rx_ready[1])
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);
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psync rx_done_0(
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.clk1(phy_rx_clk),
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.i(phy_rx_done[0]),
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.clk2(sys_clk),
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.o(sys_rx_done[0])
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);
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psync rx_done_1(
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.clk1(phy_rx_clk),
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.i(phy_rx_done[1]),
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.clk2(sys_clk),
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.o(sys_rx_done[1])
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);
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reg [10:0] sys_rx_count_0_r;
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reg [10:0] sys_rx_count_1_r;
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always @(posedge sys_clk) begin
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sys_rx_count_0_r <= phy_rx_count_0;
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sys_rx_count_0 <= sys_rx_count_0_r;
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sys_rx_count_1_r <= phy_rx_count_1;
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sys_rx_count_1 <= sys_rx_count_1_r;
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end
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psync tx_start(
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.clk1(sys_clk),
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.i(sys_tx_start),
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.clk2(phy_tx_clk),
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.o(phy_tx_start)
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);
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psync tx_done(
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.clk1(phy_tx_clk),
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.i(phy_tx_done),
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.clk2(sys_clk),
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.o(sys_tx_done)
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);
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reg [10:0] phy_tx_count_r;
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always @(posedge phy_tx_clk) begin
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phy_tx_count_r <= sys_tx_count;
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phy_tx_count <= phy_tx_count_r;
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end
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endmodule
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