131 lines
3.9 KiB
Python
131 lines
3.9 KiB
Python
from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank.description import *
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class Bank:
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def __init__(self, description, address=0, bus=None):
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self.description = description
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self.address = address
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if bus is None:
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bus = csr.Interface()
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self.bus = bus
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def get_fragment(self):
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comb = []
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sync = []
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sel = Signal()
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comb.append(sel.eq(self.bus.adr[9:] == self.address))
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desc_exp = expand_description(self.description, csr.data_width)
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nbits = bits_for(len(desc_exp)-1)
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# Bus writes
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bwcases = {}
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for i, reg in enumerate(desc_exp):
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if isinstance(reg, RegisterRaw):
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comb.append(reg.r.eq(self.bus.dat_w[:reg.size]))
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comb.append(reg.re.eq(sel & \
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self.bus.we & \
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(self.bus.adr[:nbits] == i)))
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elif isinstance(reg, RegisterFields):
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bwra = []
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offset = 0
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for field in reg.fields:
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if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
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bwra.append(field.storage.eq(self.bus.dat_w[offset:offset+field.size]))
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offset += field.size
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if bwra:
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bwcases[i] = bwra
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# commit atomic writes
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for field in reg.fields:
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if isinstance(field, FieldAlias) and field.commit_list:
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commit_instr = [hf.commit_to.eq(hf.storage) for hf in field.commit_list]
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sync.append(If(sel & self.bus.we & self.bus.adr[:nbits] == i, *commit_instr))
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else:
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raise TypeError
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if bwcases:
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sync.append(If(sel & self.bus.we, Case(self.bus.adr[:nbits], bwcases)))
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# Bus reads
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brcases = {}
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for i, reg in enumerate(desc_exp):
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if isinstance(reg, RegisterRaw):
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brcases[i] = [self.bus.dat_r.eq(reg.w)]
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elif isinstance(reg, RegisterFields):
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brs = []
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reg_readable = False
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for field in reg.fields:
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if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
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brs.append(field.storage)
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reg_readable = True
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else:
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brs.append(Replicate(0, field.size))
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if reg_readable:
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brcases[i] = [self.bus.dat_r.eq(Cat(*brs))]
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else:
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raise TypeError
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if brcases:
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sync.append(self.bus.dat_r.eq(0))
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sync.append(If(sel, Case(self.bus.adr[:nbits], brcases)))
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else:
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comb.append(self.bus.dat_r.eq(0))
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# Device access
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for reg in self.description:
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if isinstance(reg, RegisterFields):
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for field in reg.fields:
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if field.access_bus == READ_ONLY and field.access_dev == WRITE_ONLY:
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comb.append(field.storage.eq(field.w))
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else:
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if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
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comb.append(field.r.eq(field.storage))
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if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
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sync.append(If(field.we, field.storage.eq(field.w)))
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return Fragment(comb, sync)
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# address_map(name, memory) returns the CSR offset at which to map
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# the CSR object (register bank or memory).
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# If memory=None, the object is the register bank of object source.name.
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# Otherwise, it is a memory object belonging to source.name.
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# address_map is called exactly once for each object at each call to
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# scan(), so it can have side effects.
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class BankArray:
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def __init__(self, source, address_map):
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self.source = source
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self.address_map = address_map
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self.scan()
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def scan(self):
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self.banks = []
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self.srams = []
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for name, obj in self.source.__dict__.items():
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if hasattr(obj, "get_registers"):
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registers = obj.get_registers()
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else:
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registers = []
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if hasattr(obj, "get_memories"):
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memories = obj.get_memories()
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for memory in memories:
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mapaddr = self.address_map(name, memory)
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mmap = csr.SRAM(memory, mapaddr)
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registers += mmap.get_registers()
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self.srams.append(mmap)
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if registers:
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mapaddr = self.address_map(name, None)
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rmap = Bank(registers, mapaddr)
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self.banks.append(rmap)
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def get_banks(self):
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return self.banks
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def get_srams(self):
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return self.srams
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def get_buses(self):
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return [i.bus for i in self.banks + self.srams]
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def get_fragment(self):
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return sum([i.get_fragment() for i in self.banks + self.srams], Fragment())
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