Caleb Jamison 1f0b3f8124 Add ifdef check for MAIN_RAM_SIZE		2019-03-31 10:33:39 -05:00
..
boards	targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC	2019-03-05 13:27:11 +01:00
build	Merge pull request #154 from daveshah1/yosys_xilinx_edif	2019-03-22 17:43:40 +01:00
gen	gen/sim/core: add args support on Display	2018-12-09 09:46:10 +01:00
soc	Add ifdef check for MAIN_RAM_SIZE	2019-03-31 10:33:39 -05:00
utils	utils/litex_sim: fix main_ram_size	2019-03-16 21:25:02 +01:00
__init__.py	ease RemoteClient import	2018-09-23 10:23:00 +02:00