litex/litex/soc
Florent Kermarrec fbb24720f0 soc/get_mem_data: add direct support for regions
We now support passing filename (offset=0), json file and regions
2019-05-03 13:24:06 +02:00
..
cores cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant 2019-05-03 09:30:26 +02:00
integration soc/get_mem_data: add direct support for regions 2019-05-03 13:24:06 +02:00
interconnect soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone 2019-05-03 11:59:06 +02:00
software bios/boot: add liftoff banner just before booting 2019-05-02 18:26:35 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
MISOC_LICENSE litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00