155 lines
4.5 KiB
Python
155 lines
4.5 KiB
Python
from misoclib.mem.litesata.common import *
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def us(t, clk_freq):
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clk_period_us = 1000000/clk_freq
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return math.ceil(t/clk_period_us)
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class LiteSATAPHYCtrl(Module):
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def __init__(self, trx, crg, clk_freq):
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self.ready = Signal()
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self.need_reset = Signal()
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self.sink = sink = Sink(phy_description(32))
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self.source = source = Source(phy_description(32))
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# # #
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self.comb += [
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source.stb.eq(1),
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sink.ack.eq(1)
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]
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retry_timeout = Timeout(us(10000, clk_freq))
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align_timeout = Timeout(us(873, clk_freq))
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self.submodules += align_timeout, retry_timeout
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align_detect = Signal()
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non_align_cnt = Signal(4)
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self.fsm = fsm = FSM(reset_state="RESET")
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self.submodules += fsm
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fsm.act("RESET",
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trx.tx_idle.eq(1),
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retry_timeout.reset.eq(1),
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align_timeout.reset.eq(1),
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If(crg.ready,
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NextState("COMINIT")
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),
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)
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fsm.act("COMINIT",
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trx.tx_idle.eq(1),
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trx.tx_cominit_stb.eq(1),
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If(trx.tx_cominit_ack & ~trx.rx_cominit_stb,
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NextState("AWAIT_COMINIT")
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),
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)
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fsm.act("AWAIT_COMINIT",
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trx.tx_idle.eq(1),
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retry_timeout.ce.eq(1),
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If(trx.rx_cominit_stb,
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NextState("AWAIT_NO_COMINIT")
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).Else(
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If(retry_timeout.reached,
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NextState("RESET")
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)
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),
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)
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fsm.act("AWAIT_NO_COMINIT",
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trx.tx_idle.eq(1),
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retry_timeout.reset.eq(1),
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If(~trx.rx_cominit_stb,
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NextState("CALIBRATE")
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),
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)
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fsm.act("CALIBRATE",
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trx.tx_idle.eq(1),
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NextState("COMWAKE"),
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)
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fsm.act("COMWAKE",
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trx.tx_idle.eq(1),
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trx.tx_comwake_stb.eq(1),
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If(trx.tx_comwake_ack,
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NextState("AWAIT_COMWAKE")
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),
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)
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fsm.act("AWAIT_COMWAKE",
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trx.tx_idle.eq(1),
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retry_timeout.ce.eq(1),
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If(trx.rx_comwake_stb,
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NextState("AWAIT_NO_COMWAKE")
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).Else(
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If(retry_timeout.reached,
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NextState("RESET")
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)
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),
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)
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fsm.act("AWAIT_NO_COMWAKE",
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trx.tx_idle.eq(1),
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If(~trx.rx_comwake_stb,
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NextState("AWAIT_NO_RX_IDLE")
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),
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)
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fsm.act("AWAIT_NO_RX_IDLE",
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trx.tx_idle.eq(0),
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source.data.eq(0x4A4A4A4A), # D10.2
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source.charisk.eq(0b0000),
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If(~trx.rx_idle,
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NextState("AWAIT_ALIGN"),
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crg.reset.eq(1),
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trx.pmarxreset.eq(1)
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),
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)
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fsm.act("AWAIT_ALIGN",
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trx.tx_idle.eq(0),
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source.data.eq(0x4A4A4A4A), # D10.2
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source.charisk.eq(0b0000),
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trx.rx_align.eq(1),
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align_timeout.ce.eq(1),
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If(align_detect & ~trx.rx_idle,
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NextState("SEND_ALIGN")
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).Elif(align_timeout.reached,
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NextState("RESET")
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),
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)
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fsm.act("SEND_ALIGN",
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trx.tx_idle.eq(0),
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trx.rx_align.eq(1),
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source.data.eq(primitives["ALIGN"]),
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source.charisk.eq(0b0001),
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If(non_align_cnt == 3,
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NextState("READY")
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),
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)
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fsm.act("READY",
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trx.tx_idle.eq(0),
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trx.rx_align.eq(1),
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source.data.eq(primitives["SYNC"]),
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source.charisk.eq(0b0001),
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If(trx.rx_idle,
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NextState("RESET")
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),
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self.ready.eq(1),
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)
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reset_timeout = Timeout(clk_freq//16)
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self.submodules += reset_timeout
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self.comb += [
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reset_timeout.ce.eq(~self.ready),
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self.need_reset.eq(reset_timeout.reached)
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]
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self.comb += \
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align_detect.eq(self.sink.stb &
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(self.sink.data == primitives["ALIGN"]))
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self.sync += \
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If(fsm.ongoing("SEND_ALIGN"),
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If(sink.stb,
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If(sink.data[0:8] == 0x7C,
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non_align_cnt.eq(non_align_cnt + 1)
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).Else(
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non_align_cnt.eq(0)
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)
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)
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)
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