litex/migen
Sebastien Bourdeauducq fc85ca53ad actorlib/spi: do not use MemoryPort 2012-11-26 18:27:59 +01:00
..
actorlib actorlib/spi: do not use MemoryPort 2012-11-26 18:27:59 +01:00
bank bank/description: regprefix 2012-10-15 21:21:59 +02:00
bus bus: memory initiator 2012-11-23 16:22:50 +01:00
corelogic corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time 2012-07-13 20:21:04 +02:00
fhdl fhdl/structure: disable we_granularity when larger than width 2012-11-23 23:08:12 +01:00
flow fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs. 2012-11-23 18:38:03 +01:00
pytholite pytholite: fix import of _Slice 2012-11-23 21:20:18 +01:00
sim sim/generic/multiread: do not return spurious items 2012-11-23 23:07:25 +01:00
transform transform/unroll_sync: autodetect in/out 2012-10-15 20:32:07 +02:00
uio pytholite/io: support memory 2012-11-23 20:36:09 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00