419 lines
16 KiB
Python
419 lines
16 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import random
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from migen import *
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect import wishbone
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# Software Models ----------------------------------------------------------------------------------
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class Burst:
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def __init__(self, addr, type=BURST_FIXED, len=0, size=0):
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self.addr = addr
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self.type = type
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self.len = len
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self.size = size
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def to_beats(self):
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r = []
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burst_length = self.len + 1
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burst_size = 2**self.size
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for i in range(burst_length):
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if self.type == BURST_INCR:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == BURST_WRAP:
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assert burst_length in [2, 4, 8, 16]
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assert (self.addr % burst_size) == 0
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burst_base = self.addr - self.addr % (burst_length * burst_size)
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burst_offset = self.addr % (burst_length * burst_size)
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burst_addr = burst_base + (burst_offset + i*burst_size) % (burst_length * burst_size)
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#print("0x{:08x}".format(burst_addr))
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r += [Beat(burst_addr)]
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else:
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r += [Beat(self.addr)]
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return r
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class Beat:
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def __init__(self, addr):
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self.addr = addr
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class Access(Burst):
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def __init__(self, addr, data, id, **kwargs):
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Burst.__init__(self, addr, **kwargs)
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self.data = data
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self.id = id
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class Write(Access): pass
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class Read(Access): pass
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# TestAXI ------------------------------------------------------------------------------------------
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class TestAXI(unittest.TestCase):
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def test_burst2beat(self):
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def bursts_generator(ax, bursts, valid_rand=50):
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prng = random.Random(42)
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for burst in bursts:
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yield ax.valid.eq(1)
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yield ax.addr.eq(burst.addr)
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yield ax.burst.eq(burst.type)
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yield ax.len.eq(burst.len)
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yield ax.size.eq(burst.size)
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while (yield ax.ready) == 0:
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yield
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yield ax.valid.eq(0)
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while prng.randrange(100) < valid_rand:
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yield
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yield
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@passive
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def beats_checker(ax, beats, ready_rand=50):
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self.errors = 0
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yield ax.ready.eq(0)
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prng = random.Random(42)
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for beat in beats:
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while ((yield ax.valid) and (yield ax.ready)) == 0:
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if prng.randrange(100) > ready_rand:
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yield ax.ready.eq(1)
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else:
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yield ax.ready.eq(0)
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yield
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ax_addr = (yield ax.addr)
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#print("0x{:08x}".format(ax_addr))
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if ax_addr != beat.addr:
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self.errors += 1
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yield
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# DUT
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ax_burst = AXIStreamInterface(layout=ax_description(32), id_width=32)
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ax_beat = AXIStreamInterface(layout=ax_description(32), id_width=32)
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dut = AXIBurst2Beat(ax_burst, ax_beat)
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# Generate DUT input (bursts).
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2)))
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bursts.append(Burst(0x80000160, BURST_WRAP, 0x3, 0b100))
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# Generate expected DUT output (beats for reference).
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beats = []
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for burst in bursts:
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beats += burst.to_beats()
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# Simulation
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generators = [
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bursts_generator(ax_burst, bursts),
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beats_checker(ax_beat, beats)
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]
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run_simulation(dut, generators)
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self.assertEqual(self.errors, 0)
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def _test_axi2wishbone(self,
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naccesses=16, simultaneous_writes_reads=False,
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# Random: 0: min (no random), 100: max.
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# Burst randomness.
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id_rand_enable = False,
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len_rand_enable = False,
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data_rand_enable = False,
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# Flow valid randomness.
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aw_valid_random = 0,
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w_valid_random = 0,
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ar_valid_random = 0,
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r_valid_random = 0,
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# Flow ready randomness.
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w_ready_random = 0,
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b_ready_random = 0,
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r_ready_random = 0
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):
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def writes_cmd_generator(axi_port, writes):
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prng = random.Random(42)
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for write in writes:
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while prng.randrange(100) < aw_valid_random:
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yield
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# Send command.
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yield axi_port.aw.valid.eq(1)
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yield axi_port.aw.addr.eq(write.addr<<2)
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yield axi_port.aw.burst.eq(write.type)
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yield axi_port.aw.len.eq(write.len)
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yield axi_port.aw.size.eq(write.size)
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yield axi_port.aw.id.eq(write.id)
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yield
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while (yield axi_port.aw.ready) == 0:
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yield
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yield axi_port.aw.valid.eq(0)
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def writes_data_generator(axi_port, writes):
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prng = random.Random(42)
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yield axi_port.w.strb.eq(2**(len(axi_port.w.data)//8) - 1)
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for write in writes:
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for i, data in enumerate(write.data):
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while prng.randrange(100) < w_valid_random:
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yield
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# Send data.
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yield axi_port.w.valid.eq(1)
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if (i == (len(write.data) - 1)):
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yield axi_port.w.last.eq(1)
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else:
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yield axi_port.w.last.eq(0)
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yield axi_port.w.data.eq(data)
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yield
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while (yield axi_port.w.ready) == 0:
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yield
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yield axi_port.w.valid.eq(0)
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axi_port.reads_enable = True
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def writes_response_generator(axi_port, writes):
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prng = random.Random(42)
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self.writes_id_errors = 0
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for write in writes:
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# wait response
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yield axi_port.b.ready.eq(0)
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yield
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while (yield axi_port.b.valid) == 0:
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yield
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while prng.randrange(100) < b_ready_random:
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yield
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yield axi_port.b.ready.eq(1)
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yield
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if (yield axi_port.b.id) != write.id:
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self.writes_id_errors += 1
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def reads_cmd_generator(axi_port, reads):
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prng = random.Random(42)
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while not axi_port.reads_enable:
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yield
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for read in reads:
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while prng.randrange(100) < ar_valid_random:
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yield
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# Send command.
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yield axi_port.ar.valid.eq(1)
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yield axi_port.ar.addr.eq(read.addr<<2)
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yield axi_port.ar.burst.eq(read.type)
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yield axi_port.ar.len.eq(read.len)
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yield axi_port.ar.size.eq(read.size)
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yield axi_port.ar.id.eq(read.id)
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yield
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while (yield axi_port.ar.ready) == 0:
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yield
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yield axi_port.ar.valid.eq(0)
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def reads_response_data_generator(axi_port, reads):
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prng = random.Random(42)
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self.reads_data_errors = 0
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self.reads_id_errors = 0
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self.reads_last_errors = 0
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while not axi_port.reads_enable:
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yield
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for read in reads:
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for i, data in enumerate(read.data):
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# Wait data / response.
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yield axi_port.r.ready.eq(0)
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yield
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while (yield axi_port.r.valid) == 0:
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yield
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while prng.randrange(100) < r_ready_random:
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yield
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yield axi_port.r.ready.eq(1)
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yield
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if (yield axi_port.r.data) != data:
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self.reads_data_errors += 1
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if (yield axi_port.r.id) != read.id:
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self.reads_id_errors += 1
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if i == (len(read.data) - 1):
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if (yield axi_port.r.last) != 1:
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self.reads_last_errors += 1
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else:
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if (yield axi_port.r.last) != 0:
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self.reads_last_errors += 1
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# DUT
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class DUT(Module):
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def __init__(self):
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self.axi = AXIInterface(data_width=32, address_width=32, id_width=8)
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self.wishbone = wishbone.Interface(data_width=32, adr_width=30)
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axi2wishbone = AXI2Wishbone(self.axi, self.wishbone)
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self.submodules += axi2wishbone
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wishbone_mem = wishbone.SRAM(1024, bus=self.wishbone)
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self.submodules += wishbone_mem
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dut = DUT()
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# Generate writes/reads.
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prng = random.Random(42)
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writes = []
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offset = 1
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for i in range(naccesses):
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_id = prng.randrange(2**8) if id_rand_enable else i
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_len = prng.randrange(32) if len_rand_enable else i
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_data = [prng.randrange(2**32) if data_rand_enable else j for j in range(_len + 1)]
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writes.append(Write(offset, _data, _id, type=BURST_INCR, len=_len, size=log2_int(32//8)))
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offset += _len + 1
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# Dummy reads to ensure datas have been written before the effective reads start.
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dummy_reads = [Read(1023, [0], 0, type=BURST_FIXED, len=0, size=log2_int(32//8)) for _ in range(32)]
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reads = writes
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# Simulation
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if simultaneous_writes_reads:
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dut.axi.reads_enable = True
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else:
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dut.axi.reads_enable = False # Will be set by writes_data_generator.
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generators = [
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writes_cmd_generator(dut.axi, writes),
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writes_data_generator(dut.axi, writes),
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writes_response_generator(dut.axi, writes),
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reads_cmd_generator(dut.axi, reads),
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reads_response_data_generator(dut.axi, reads)
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]
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run_simulation(dut, generators)
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self.assertEqual(self.writes_id_errors, 0)
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self.assertEqual(self.reads_data_errors, 0)
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self.assertEqual(self.reads_id_errors, 0)
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self.assertEqual(self.reads_last_errors, 0)
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# Test with no randomness.
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def test_axi2wishbone_writes_then_reads_no_random(self):
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self._test_axi2wishbone(simultaneous_writes_reads=False)
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# Test randomness one parameter at a time.
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def test_axi2wishbone_writes_then_reads_random_bursts(self):
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self._test_axi2wishbone(
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simultaneous_writes_reads = False,
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id_rand_enable = True,
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len_rand_enable = True,
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data_rand_enable = True)
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def test_axi2wishbone_random_w_ready(self):
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self._test_axi2wishbone(w_ready_random=90)
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def test_axi2wishbone_random_b_ready(self):
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self._test_axi2wishbone(b_ready_random=90)
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def test_axi2wishbone_random_r_ready(self):
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self._test_axi2wishbone(r_ready_random=90)
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def test_axi2wishbone_random_aw_valid(self):
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self._test_axi2wishbone(aw_valid_random=90)
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def test_axi2wishbone_random_w_valid(self):
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self._test_axi2wishbone(w_valid_random=90)
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def test_axi2wishbone_random_ar_valid(self):
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self._test_axi2wishbone(ar_valid_random=90)
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def test_axi2wishbone_random_r_valid(self):
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self._test_axi2wishbone(r_valid_random=90)
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# Now let's stress things a bit... :)
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def test_axi2wishbone_random_all(self):
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self._test_axi2wishbone(
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simultaneous_writes_reads = False,
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id_rand_enable = True,
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len_rand_enable = True,
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aw_valid_random = 50,
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w_ready_random = 50,
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b_ready_random = 50,
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w_valid_random = 50,
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ar_valid_random = 90,
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r_valid_random = 90,
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r_ready_random = 90
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)
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def test_axi_width_converter(self):
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class DUT(Module):
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def __init__(self, dw_from=64, dw_to=32):
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self.axi_master = axi_master = AXIInterface(data_width=dw_from)
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self.axi_slave = axi_slave = AXIInterface(data_width=dw_to)
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converter = AXIConverter(axi_master, axi_slave)
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self.submodules += converter
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wb = wishbone.Interface(data_width=dw_to, address_width=axi_slave.address_width)
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axi2wb = AXI2Wishbone(axi_slave, wb)
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self.submodules += axi2wb
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self.mem = mem = wishbone.SRAM(1024, bus=wb, init=range(256))
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self.submodules += mem
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class DUT_ref(Module):
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"""
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An alternative configuration to the DUT above not using AXIConverter
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to demonstrate that the generators below are valid.
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Not used by default.
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"""
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def __init__(self, dw_from=64, dw_to=32):
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self.axi_master = axi_master = AXIInterface(data_width=dw_from)
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wb_from = wishbone.Interface(data_width=dw_from, address_width=axi_master.address_width)
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axi2wb = AXI2Wishbone(axi_master, wb_from)
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self.submodules += axi2wb
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wb_to = wishbone.Interface(data_width=dw_to, address_width=axi_master.address_width)
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wb2wb = wishbone.Converter(wb_from, wb_to)
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self.submodules += wb2wb
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self.mem = mem = wishbone.SRAM(1024, bus=wb_to, init=range(256))
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self.submodules += mem
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def generator_rd(dut):
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axi_port = dut.axi_master
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addr = 0x34
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yield axi_port.ar.addr.eq(addr * dut.mem.bus.data_width // 8)
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yield axi_port.ar.valid.eq(1)
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yield axi_port.ar.burst.eq(0)
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yield axi_port.ar.len.eq(0)
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yield axi_port.ar.size.eq(log2_int(axi_port.data_width // 8))
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yield axi_port.r.ready.eq(1)
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yield
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while (yield axi_port.r.valid) == 0:
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yield
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rd = (yield axi_port.r.data)
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mem_content = 0
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i = 0
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while i < axi_port.data_width // dut.mem.bus.data_width:
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mem_content |= (yield dut.mem.mem[addr + i]) << (i * dut.mem.bus.data_width)
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i += 1
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assert rd == mem_content, (hex(rd), hex(mem_content))
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def generator_wr(dut):
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axi_port = dut.axi_master
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addr = 0x24
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data = 0x98761244
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yield axi_port.aw.addr.eq(addr * 4)
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yield axi_port.aw.valid.eq(1)
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yield axi_port.aw.burst.eq(0)
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yield axi_port.aw.len.eq(0)
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yield axi_port.aw.size.eq(log2_int(axi_port.data_width // 8))
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yield axi_port.w.strb.eq(2**(len(axi_port.w.data)//8) - 1)
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yield axi_port.w.data.eq(data)
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yield axi_port.w.valid.eq(1)
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yield axi_port.w.last.eq(1)
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yield
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while (yield axi_port.aw.ready) == 0:
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yield
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yield axi_port.aw.valid.eq(0)
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while (yield axi_port.w.ready) == 0:
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yield
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yield axi_port.w.valid.eq(0)
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mem_content = 0
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i = 0
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while i < axi_port.data_width // dut.mem.bus.data_width:
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mem_content |= (yield dut.mem.mem[addr + i]) << (i * dut.mem.bus.data_width)
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i += 1
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assert data == mem_content, (hex(data), hex(mem_content))
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#dut = DUT(64, 32)
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dut = DUT_ref(64, 32)
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run_simulation(dut, [generator_rd(dut), generator_wr(dut)], vcd_name="sim.vcd")
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