38 lines
996 B
Python
38 lines
996 B
Python
from migen import *
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# A slightly more elaborate counter.
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# Has a clock enable (CE) signal, counts on more bits
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# and resets with a negative number.
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class Counter(Module):
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def __init__(self):
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self.ce = Signal()
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# Demonstrate negative numbers and signals larger than 32 bits.
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self.count = Signal((37, True), reset=-5)
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self.sync += If(self.ce, self.count.eq(self.count + 1))
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def counter_test(dut):
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for cycle in range(20):
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# Only assert CE every second cycle.
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# => each counter value is held for two cycles.
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if cycle % 2:
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yield dut.ce, 0 # This is how you write to a signal.
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else:
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yield dut.ce, 1
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print("Cycle: {} Count: {}".format(cycle, (yield dut.count)))
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yield
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# Output is:
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# Cycle: 0 Count: -5
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# Cycle: 1 Count: -5
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# Cycle: 2 Count: -4
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# Cycle: 3 Count: -4
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# Cycle: 4 Count: -3
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# ...
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if __name__ == "__main__":
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dut = Counter()
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Simulator(dut, counter_test(dut)).run()
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