139 lines
5.2 KiB
Python
139 lines
5.2 KiB
Python
# This file is Copyright (c) 2015 William D. Jones <thor0505@comcast.net>
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# License: BSD
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from migen.build.generic_platform import *
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from migen.build.xilinx import XilinxPlatform
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from migen.build.xilinx.programmer import XC3SProg
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_io = [
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("clk50", 0, Pins("P43"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("P41"), IOStandard("LVTTL")),
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# The serial interface and flash memory have a shared SPI bus.
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# FPGA is secondary
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("spiserial", 0,
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Subsignal("cs_n", Pins("P39"), IOStandard("LVTTL")),
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Subsignal("clk", Pins("P53"), IOStandard("LVTTL")),
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Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")),
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Subsignal("miso", Pins("P51"), IOStandard("LVTTL"))
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),
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# FPGA is primary
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("spiflash", 0,
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Subsignal("cs_n", Pins("P27"), IOStandard("LVTTL")),
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Subsignal("clk", Pins("P53"), IOStandard("LVTTL")),
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Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")),
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Subsignal("miso", Pins("P51"), IOStandard("LVTTL"))
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),
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("spiflash2x", 0,
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Subsignal("cs_n", Pins("P27")),
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Subsignal("clk", Pins("P53")),
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Subsignal("dq", Pins("P46", "P51")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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# ADC over SPI- FPGA is primary
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("adc", 0,
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Subsignal("cs_n", Pins("P12"), IOStandard("LVTTL")),
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Subsignal("clk", Pins("P9"), IOStandard("LVTTL")),
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Subsignal("mosi", Pins("P10"), IOStandard("LVTTL")),
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Subsignal("miso", Pins("P21"), IOStandard("LVTTL"))
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),
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# GPIO control- SRAM and connectors are shared: these pins control how
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# to access each. Recommended to combine with gpio_sram_bus extension,
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# since these pins are related but not exposed on connectors.
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("gpio_ctl", 0,
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Subsignal("ce_n", Pins("P3")), # Memory chip-enable. Called MEM_CEN
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# in schematic.
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Subsignal("bussw_oe_n", Pins("P30")), # 5V tolerant GPIO is shared
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# w/ memory using this pin.
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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)
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]
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# Perhaps define some connectors as having a specific purpose- i.e. a 5V GPIO
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# bus with data, peripheral-select, and control signals?
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_connectors = [
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("GPIO", """P59 P60 P61 P62 P64 P57
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P56 P52 P50 P49 P85 P84
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P83 P78 P77 P65 P70 P71
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P72 P73 P5 P4 P6 P98
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P94 P93 P90 P89 P88 P86"""), # 5V I/O- LVTTL
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("DIO", "P20 P32 P33 P34 P35 P36 P37"), # Fast 3.3V IO (Directly attached
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# to FPGA)- LVCMOS33
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("CLKIO", "P40 P44"), # Clock IO (Can be used as GPIO)- LVCMOS33
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("INPUT", "P68 P97 P7 P82"), # Input-only pins- LVCMOS33
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("LED", "P13 P15 P16 P19") # LEDs can be used as pins as well- LVTTL.
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]
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# Some default useful extensions- use platform.add_extension() to use, e.g.
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# from migen.build.platforms import mercury
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# plat = mercury.Platform()
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# plat.add_extension(mercury.gpio_sram)
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# SRAM and 5V-tolerant I/O share a parallel bus on 200k gate version. The SRAM
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# controller needs to take care of switching the bus between the two. Meant to
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# be Cat() into one GPIO bus, and combined with gpio_ctl.
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gpio_sram = [
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("gpio_sram_bus", 0,
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Subsignal("a", Pins("""GPIO:0 GPIO:1 GPIO:2 GPIO:3
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GPIO:4 GPIO:5 GPIO:6 GPIO:7
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GPIO:8 GPIO:9 GPIO:10 GPIO:11
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GPIO:12 GPIO:13 GPIO:14 GPIO:15
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GPIO:16 GPIO:17 GPIO:18 GPIO:19""")),
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# A19 is actually unused- free for GPIO
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# 8-bit data bus
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Subsignal("d", Pins("""GPIO:20 GPIO:21 GPIO:22 GPIO:23
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GPIO:24 GPIO:25 GPIO:26 GPIO:27""")),
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Subsignal("we_n", Pins("GPIO:28")),
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Subsignal("unused", Pins("GPIO:29")), # Only used by GPIO.
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# Subsignal("oe_n", Pins()), # If OE wasn't tied to ground on Mercury,
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# this pin would be here.
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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)
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]
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# The "serial port" is in fact over SPI. The creators of the board provide a
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# VHDL file for talking over this interface. In light of space constraints and
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# the fact that both the FT245RL and FPGA can BOTH be SPI primaries, however,
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# it may be necessary to sacrifice two "high-speed" (DIO, INPUT) pins instead.
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serial = [
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("serial", 0,
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Subsignal("tx", Pins("DIO:0"), IOStandard("LVCMOS33")), # FTDI D1
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Subsignal("rx", Pins("INPUT:0"), IOStandard("LVCMOS33"))
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) # FTDI D0
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]
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leds = [
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("user_led", 0, Pins("LED:0"), IOStandard("LVTTL")),
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("user_led", 1, Pins("LED:1"), IOStandard("LVTTL")),
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("user_led", 2, Pins("LED:2"), IOStandard("LVTTL")),
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("user_led", 3, Pins("LED:3"), IOStandard("LVTTL"))
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]
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# See: http://www.micro-nova.com/mercury-baseboard/
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# Not implemented yet.
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baseboard = [
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 20
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def __init__(self, device="xc3s200a-4-vq100"):
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XilinxPlatform.__init__(self, device, _io, _connectors)
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# Small device- optimize for AREA instead of SPEED (LM32 runs at about
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# 60-65MHz in AREA configuration).
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self.toolchain.xst_opt = """-ifmt MIXED
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-use_new_parser yes
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-opt_mode AREA
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-register_balancing yes"""
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def create_programmer(self):
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raise NotImplementedError
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