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litex/litesata
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Florent Kermarrec ff0c8e3d22 add PacketBuffer, simplify architecture and reduce ressource usage
2015-01-22 00:13:19 +01:00
..
core add PacketBuffer, simplify architecture and reduce ressource usage 2015-01-22 00:13:19 +01:00
frontend add PacketBuffer, simplify architecture and reduce ressource usage 2015-01-22 00:13:19 +01:00
phy add verilog backend to use the core with a "standard" flow 2015-01-19 20:38:48 +01:00
test add PacketBuffer, simplify architecture and reduce ressource usage 2015-01-22 00:13:19 +01:00
__init__.py add PacketBuffer, simplify architecture and reduce ressource usage 2015-01-22 00:13:19 +01:00
common.py add PacketBuffer, simplify architecture and reduce ressource usage 2015-01-22 00:13:19 +01:00